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[F28069] Fault trigger at analog comparator module

Brian Chang90901
Intellectual 2540 points

Hi Champs,

We get problem at using  analog comparator to trigger EPWM TZ interrupt. The condition should not happen and we can not observe the input volage is hugh enough to trigger the comparator. The comparator trigger level was set to 1.8V but the monitoring  voltage is under 500mV when the TZ  ISR happen.

Ch2: the analog comparator input A2  Ch4: toggle IO at ePWM1 TZ ISR   

 

We tried to debug it and we fund two condition the failure will not happen

1.  Disable the comparator directly

2.  Set the trigger level to 1023.

Both cases show that problem should be related with the analog comparator module only. The comparator was initialized only after hardware rest.

We already set the qualication window to 16 clock and large blanking window. However that is not helpful for this issue.

The problem was we can not find the signal which can trigger the fault so we did not know how to improve it at hardware.

Did you have any suggestion or comment why and what we can observe any falirure signal by some point??

Thanks

BR

Brian

  • 0
    TI__Guru 57255 points

    Hi Brian,

    To help debug this, I might recommend bringing the comparator output to a GPIO pin and viewing it with the other waveforms.   

    This will help us decide whether the issue is occurring because of the comparator peripheral or because of the ePWM peripheral (TZ portion).

    COMPxOUT is a GPIO mux option at several GPIO pins.


    Thank you,
    Brett

  • 0
    TI__Guru 62975 points

    Brian,

    Are there any filtering components on the comparator input (A2) signal path?  Any resistors or capacitors?  If so, were the waveforms captured before or after the filtering components?

    Is comparator hysteresis enabled?  If so, does the behavior change when hysteresis is disabled?

    Do you have the option of driving the comparator negative input directly with an external reference voltage?  This would help to eliminate the internal DAC reference as a possible source of error.

    -Tommy

  • 0 in reply to tlee
    TI__Intellectual 2540 points
    Hi Tommy,
    The signal is coming from current transformer and there is input resistor 220 ohm before A2. The testing waveform was measured at c2000 pin.

    Yes, we also try to disable the hysteresis already. When we disable the hysteresis , the failure still happen but one thing change.
    The test condition was the loading off for the system.
    The failure happened at loading was increasing more after disable hysteresis.
    We thought that is the as same as the condition we tried to increase the DAC value.

    I am not understand how to inject the negative input. Can you explan more detail about that ?


    Hi Brett,

    When turning off the comparator or set the high DAC value , the failure didn't happen.
    That already prove the condition was related with comparator.
    I would try to confirm with customer because they use every pin already.
    I am not sure the COMP2OUT can be used.

    Thanks
    BR
    Brian
  • 0 in reply to Brian Chang90901
    TI__Guru 62975 points

    Brian,

    By driving the negative comparator input, I mean driving COMP1B (pin B2) directly after setting the COMPSOURCE bit.

    Since the spurious trips worsen when you disable hysteresis, I suspect that there may be noise on the comparator input.  Would it be possible to take some additional scope shots with a smaller time scale?  The original scope shot appears to be set to 200us / div.  Can you get closer to 1us / div?

    The comparator response time in the datasheet is ~30ns so we may be looking for a voltage glitch with a very short duration.  Since you see trips when the qualification stage is enabled, a potential glitch would probably be a few hundred ns in duration.

    -Tommy

  • 0 in reply to tlee
    TI__Intellectual 2540 points
    Hi Tommy

    The qualification was 16 so the glitch signal should be 35x nsec ( 16 * 1/45Mhz). I would check with customer if we can have pin to be COMPXOUT function and use it for trigger source of scope.

    By the way , for negative comparator input input , are you suggesting to always have a small negative voltage at B2 for testing ??

    BR
    Brian
  • 0 in reply to Brian Chang90901
    TI__Guru 62975 points
    Brian,

    For the COMP1B input, I mean to replace the internal reference DAC with an external reference voltage.

    For example, if the application was originally setting a trip-point near 1.65V by programming DACVAL to 511, the experiment would be to change the COMPSOURCE to external and drive the 1.65V reference onto COMP1B externally. It might be easier to see how the comparator is generating trips when both signals are visible.

    -Tommy
  • 0 in reply to tlee
    TI__Intellectual 2540 points

    Hi Tommy and Brett,  

    As previous suggestion , we had monitoring the singal by using the comp out pin.

    Ch1: 12V output (PSFB DC/DC)  Ch2 :  analog comparator input (A4)  Ch3: COMP2OUT

     

    We tried to use more big time scale (1us) and the capture was as bellowing. That show the comparator output result.

    Ch1: 12V output (PSFB DC/DC)  Ch2 :  analog comparator input (A4)  Ch3: COMP2OUT

    We can not use extenal reference for b channel pin because all the adc pin was used....

    BR

    Brian  

  • 0 in reply to Brian Chang90901
    TI__Guru 62975 points

    Brian,

    This really is strange.  Is this behavior seen on multiple boards?  Are we confident that nothing in the software is changing the comparator register settings?  Is the ramp generator enabled?

    It looks to me like the comparator is only misbehaving during a very small period of time.  Is this correct?

    Is there any noise visible on the VDDA & VSSA supplies?  Noise on these supplies can directly influence the internal reference voltage for the comparator.

    -Tommy

  • 0 in reply to tlee
    TI__Intellectual 2540 points

    Tommy,

    I  thought that was very strange and the behavior was fund at serveral unit.

    1.  I had search customer's code and we confirm the comparator  was only configured after power on reset.

        Even though the failure happen ,  the system is still working normal. If the register was been written  , the system should not be work.

    2. the ramp generator didn't use.  The setting was using DAC directly.

    3.  It looks that the comparator fault triggering as the posted waveform. Only at that timng.

    As we mention , this failure was happening during the PSFB DC/DC load off. For V33A , it was also actomg as load off.

    For nosie , we didn't see the big noise

      Ch2: V33A   Ch4 : Debug IO  togging at PWM TZ ISR

    However , as we mention , the V33A was also working as load off.

    The V33A will be larger during this operation ( 3.275 V-> 3.291V).

    However, that is under spec..

      Ch2: V33A   Ch4 : Debug IO  togging at PWM TZ ISR

    The timing of failure was very consistent . It happen after the V33A was raising .

    I am not sure that would be a information or not.

    BR

    Brian

  • 0 in reply to Brian Chang90901
    TI__Guru 62975 points

    Brian,

    I don't have any explanations for the behavior based on our current set of information so any observations are welcome.  I'll collaborate with some others here to see if we can think of anything.

    -Tommy

  • 0 in reply to tlee
    TI__Mastermind 28275 points

    Brian,

    The comparator will misbehave if there is noise on VDDA/VSSA, inverting input and non-inverting input. Your problem will be a little hard to debug since it sounds like you don't have a lot of flexibility in what you can change on the hardware so to quickly summarize what we know about your hardware setup:

    1. You can monitor VDDA/VSSA.

    2. You can monitor non-inverting input.

    3. You can't monitor inverting input or drive it externally.

    Since you provided scope shots for 1 & 2 and none of them can explain what you are seeing, that leaves point 3. I know you already mentioned the inverting input is used as ADC input. If you know the signal profile on the ADC input, you might still be able to debug point 3. Two questions for you:

    1. What is the signal profile on the ADC input (B2)? If it is steady enough and far away from the trip point, you could still make that the source for the inverting input and that might give some insight into what is happening.

    2. Do you have any bandwidth filtering enabled on the scope channels? This can sometimes mask out fast glitches.