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OSHTSYNC bit, SELFCLRTRREM bit in TBCTL2 register on Page 1547 of TMS320F2837xS Delfino Microcontrollers Technical Reference Manual SPRUHX5C

mao peng
Intellectual 490 points

Where can I find explanation of OSHTSYNC bit and SELFCLRTRREM bit in TBCTL2 register.

what does sentence "Allow one sync pulse to propogate" and "Loop back sync pulse to enable self sync operation" mean?

  • 0
    TI__Mastermind 24095 points
    Hi Mao,

    More details need to be added for this bit and the explanation of the functionality of this bit is not clear.
    I'll raise a documentation update request for this.

    -Bharathi.
  • 0 in reply to Subrahmanya
    Intellectual 490 points

    Dear Bharathi,

    Thanks for your reply.

    Peng Mao

  • 0
    Prodigy 170 points

    Just our experienceabout OSHTSYNC:
    - It does what the name says. When properly enabled and armed it allows only one sync pulse to pass.
    - One sync pulse is really only one sync pulse, we tried different things to rearm it without success.
    - You need some luck to enable it. Probably some Flags need to cleared before (TBSTS.SYNCI ?).
    - When initialization fails it jams the sync, making it a ZeroShotSync.
    Our Conclusion:
    Without proper documentation it is to unpredictable.

    Does anyone else got it working reliable?


    Edit:

    Most problems have been caused by the debugger. Probably the OSHTSYNC is working as expected.

  • 0 in reply to johannes.droege
    TI__Expert 5940 points
    Hello,

    If you still have a question, please consider creating a new post as old posts are generally closed and no longer tracked. You can provide the necessary information regarding your issue in the new post and include a link to this post if you'd like.

    Thanks,
    Elizabeth