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Allocating Data memory for CLA?

Prakash Kumar Thulasi Kumar
Expert 2015 points

Hi Guys,

CCS v 6.1.3.0034 (compiler version = TI v15.12.1.LTS)

TMX320F28075 Control Card

control Suite v 3.4.0

In the 2807x_FLASH_CLA_lnk_cpu1.cmd file, the following code is written:

   Cla1Prog         : LOAD = FLASHD,
                      RUN = RAMLS5,
                      LOAD_START(_Cla1funcsLoadStart),
                      LOAD_END(_Cla1funcsLoadEnd),
                      RUN_START(_Cla1funcsRunStart),
                      LOAD_SIZE(_Cla1funcsLoadSize),
                      PAGE = 0, ALIGN(4)

   CLADataLS0		: > RAMLS0, PAGE=1
   CLADataLS1		: > RAMLS1, PAGE=1

RAMLS5 is allocated as Program Memory and LS0 and LS1 are allocated as data memory.

So can I skip the memory configuration for CLA, i.e can I skip the following code?

	EALLOW;

	// Initialize and wait for CLA1ToCPUMsgRAM
	MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
	while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};

	// Initialize and wait for CPUToCLA1MsgRAM
	MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
	while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};

	/* Filter1 and Filter2 data memory LS0 */
	MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1;    //LS2RAM is shared between CPU and CLA
	MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0;    //LS2RAM is configured as data memory

	/* Filter3 and Filter4 data memory LS1 */
	MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1;    //LS3RAM is shared between CPU and CLA
	MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0;    //LS3RAM is configured as data memory

	MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;    //LS5RAM is shared between CPU and CLA
	MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;    //LS5RAM is configured as program memory

	EDIS;

  • 0
    TI__Guru* 91275 points
    Prakash,

    The linker command file (.cmd) only tells the tools (compiler, assembler, linker) where you intend to run the code. It uses this information to assign addresses appropriately.

    The code fragments you posted configure the memory on the device itself at runtime so it is then possible to use the blocks as you intended.

    Hope that helps.
    Lori
  • 0 in reply to Lori Heustess
    Expert 2015 points
    Hi Lori,
    Thanks for the reply.
    So, can I use the 2807x_FLASH_CLA_lnk_cpu1.cmd file and at the same time configure LS0 and LS1 as program memory and LS3, LS4 and LS5 as data memory?
    Will this cause problem, because LS0 is configured as data memory in cmd file and I configure it again as program memory?
  • 0 in reply to Prakash Kumar Thulasi Kumar
    TI__Mastermind 20850 points

    Hi Prakash,

    Prakash Kumar Thulasi Kumar said:
    So, can I use the 2807x_FLASH_CLA_lnk_cpu1.cmd file and at the same time configure LS0 and LS1 as program memory and LS3, LS4 and LS5 as data memory?

    Yes that is correct. The memory is unified so it will work. You can always move RAMLS0 from the data page to the program page in the linker command file. I believe its only an issue for the debugger - CCS will not show the right data......there is an E2E post on that but i cant seem to find it now.

    Prakash Kumar Thulasi Kumar said:
    Will this cause problem, because LS0 is configured as data memory in cmd file and I configure it again as program memory?

    No, it will work. But if you see weirdness with the CCS debug windows move LS0 over to the program page in the cmd file.