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Hi Guys,
CCS v 6.1.3.0034 (compiler version = TI v15.12.1.LTS)
TMX320F28075 Control Card
control Suite v 3.4.0
In the 2807x_FLASH_CLA_lnk_cpu1.cmd file, the following code is written:
Cla1Prog : LOAD = FLASHD,
RUN = RAMLS5,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0, ALIGN(4)
CLADataLS0 : > RAMLS0, PAGE=1
CLADataLS1 : > RAMLS1, PAGE=1RAMLS5 is allocated as Program Memory and LS0 and LS1 are allocated as data memory.
So can I skip the memory configuration for CLA, i.e can I skip the following code?
EALLOW;
// Initialize and wait for CLA1ToCPUMsgRAM
MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};
// Initialize and wait for CPUToCLA1MsgRAM
MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};
/* Filter1 and Filter2 data memory LS0 */
MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1; //LS2RAM is shared between CPU and CLA
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0; //LS2RAM is configured as data memory
/* Filter3 and Filter4 data memory LS1 */
MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1; //LS3RAM is shared between CPU and CLA
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0; //LS3RAM is configured as data memory
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1; //LS5RAM is shared between CPU and CLA
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1; //LS5RAM is configured as program memory
EDIS;
