Tool/software: TI C/C++ Compiler
We have an issue in the size the CLA linker allocates:
situation1:
#pragma DATA_SECTION(CH_Bits, "Cla1ToCpuMsgRAM")
#pragma DATA_ALIGN(CH_Bits, 4)
volatile uint16_t CH_Bits;
#pragma DATA_SECTION(CH_Sample_Array, "Cla1ToCpuMsgRAM")
#pragma DATA_ALIGN(CH_Sample_Array, 4)
volatile int16_t CH_Sample_Array[41];
#pragma DATA_SECTION(CH_Sample_Array1, "Cla1ToCpuMsgRAM")
#pragma DATA_ALIGN(CH_Sample_Array1, 4)
volatile int16_t CH_Sample_Array1[41];
Allocated size by linker: 105
Situation2 : Total size of the variables are the samel
#pragma DATA_SECTION(CH_Bits, "Cla1ToCpuMsgRAM")
#pragma DATA_ALIGN(CH_Bits, 4)
volatile uint16_t CH_Bits;
#pragma DATA_SECTION(CH_Sample_Array, "Cla1ToCpuMsgRAM")
#pragma DATA_ALIGN(CH_Sample_Array, 4)
volatile int16_t CH_Sample_Array[41][2];
allocated size by linker: 146. Somehow the linker has a problem with 2 dimensional arrays
also volatile int16_t CH_Sample_Array[2][41]; gives the same problem.
And why can I not change the layout?