Part Number: TMS320F280049
Hi,
Im trying to get code that was working in the F28069 MCU and do a build in matlab R2020b for the F280049M chip. I do realize for this version of matlab that the CLA can only be built in non-external mode.
The “cla_subsystem” trigger function code generation is set to the following:
- Function packaging: non-reusable function
- Memory sections set to Cla1DataRam
- Using a custom linker command file as identified below.
I’m running into the following error even though the same contents fit within the Cla1ToCpuMsgRam in the F28069 fine:
warning: creating output section "Cla1DataRam0" without a SECTIONS
specification
"C:/svn/test_280049/trunk/28004x_cla_flash_lnk.cmd", line 114: error: program
will not fit into available memory. run placement with alignment/blocking
fails for section "Cla1ToCpuMsgRAM" size 0xb0 page 1. Available memory
ranges:
CLA1_MSGRAMLOW size: 0x7f unused: 0x7f max hole: 0x7f
Is there something in the linker file I need to change? I used a std linker command file that came with TI for the f28004x and grouped together sections to get through some compilation errors.
Latest linker command file:
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x084000, length = 0x000002
APPHDR : origin = 0x084002, length = 0x00000C
RAMM0 : origin = 0x0000F6, length = 0x00030A
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1_7 : origin = 0x008800, length = 0x0037F8
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
/* BANK 0 */
FLASH_BANK0_SEC0_RSVD : origin = 0x08000E, length = 0x000FF2 /* on-chip Flash */
FLASH_BANK0_SEC1_RSVD : origin = 0x081000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC2_RSVD : origin = 0x082000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC3_RSVD : origin = 0x08300E, length = 0x000FF2 /* on-chip Flash */
FLASH_BANK0_SEC415 : origin = 0x08400E, length = 0x00BFF1
/* BANK 1 */
FLASH_BANK1_SEC0_RSVD : origin = 0x090000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC1_RSVD : origin = 0x091000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC2_RSVD : origin = 0x092000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC3_RSVD : origin = 0x093000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC4_RSVD : origin = 0x094000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC5_RSVD : origin = 0x095000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC6_RSVD : origin = 0x096000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC7_RSVD : origin = 0x097000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC8_RSVD : origin = 0x098000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC9_RSVD : origin = 0x099000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC10_RSVD : origin = 0x09A000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC11_RSVD : origin = 0x09B000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC12_RSVD : origin = 0x09C000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC13_RSVD : origin = 0x09D000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC14_RSVD : origin = 0x09E000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC15_RSVD : origin = 0x09F000, length = 0x001000 /* on-chip Flash */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0000F5, length = 0x00030B
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMLS0_TAGS : origin = 0x008000, length = 0x000004
RAMLS0 : origin = 0x008004, length = 0x0007FC
RAMLS1_7 : origin = 0x008800, length = 0x0037F8
RAMGS0 : origin = 0x00C000, length = 0x002000
RAMGS1 : origin = 0x00E000, length = 0x002000
RAMGS2 : origin = 0x010000, length = 0x002000
RAMGS3 : origin = 0x012000, length = 0x001FF8
// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x00007F
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x00007F
}
SECTIONS
{
.cinit : > FLASH_BANK0_SEC1_RSVD, PAGE = 0, ALIGN(4)
.text : >>FLASH_BANK0_SEC415, PAGE = 0, ALIGN(4)
codestart : > BEGIN, PAGE = 0, ALIGN(4), { __APP_ENTRY = .;}
.stack : > RAMM1 PAGE = 1
.switch : > FLASH_BANK0_SEC1_RSVD, PAGE = 0, ALIGN(4)
#if defined(__TI_EABI__)
.init_array : > FLASH_BANK0_SEC1_RSVD, PAGE = 0, ALIGN(4)
.bss : > RAMLS1_7, PAGE = 1
.bss:output : > RAMLS1_7, PAGE = 1
.bss:cio : > RAMLS1_7, PAGE = 1
.data : > RAMLS1_7, PAGE = 1
.sysmem : > RAMLS1_7, PAGE = 1
.const : > FLASH_BANK0_SEC415, PAGE = 0, ALIGN(4)
#else
.pinit : > FLASH_BANK0_SEC1_RSVD, PAGE = 0, ALIGN(4)
.ebss : >>RAMLS1_7, PAGE = 1
.esysmem : > RAMLS1_7, PAGE = 1
.cio : > RAMLS1_7, PAGE = 1
.econst : > FLASH_BANK0_SEC415, PAGE = 0, ALIGN(4)
#endif
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
dclfuncs : > FLASH_BANK0_SEC1_RSVD, PAGE = 0, ALIGN(4)
#if defined(__TI_EABI__)
/* CLA specific sections */
Cla1Prog : LOAD = FLASH_BANK0_SEC415,
RUN = RAMLS0,
LOAD_START(_Cla1funcsLoadStart),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0, ALIGN(4)
#else
/* CLA specific sections */
Cla1Prog : LOAD = FLASH_BANK0_SEC415,
RUN = RAMLS0,
LOAD_START(_Cla1ProgLoadStart),
RUN_START(_Cla1ProgRunStart),
LOAD_SIZE(_Cla1ProgLoadSize),
PAGE = 0, ALIGN(4)
#endif
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
#if defined(__TI_EABI__)
.TI.ramfunc : LOAD = FLASH_BANK0_SEC1_RSVD,
RUN = RAMLS1_7
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#else
.TI.ramfunc : LOAD = FLASH_BANK0_SEC1_RSVD,
RUN = RAMLS1_7
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#endif
.scratchpad : > RAMLS1_7, PAGE = 1
.bss_cla : > RAMLS1_7, PAGE = 1
Cla1DataRam : > RAMLS1_7, PAGE = 1
cla_shared : > RAMLS1_7, PAGE = 1
CLADataLS1 : > RAMLS1_7, PAGE = 1
#if defined(__TI_EABI__)
.const_cla : LOAD = FLASH_BANK0_SEC2_RSVD,
RUN = RAMLS1_7,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize),
PAGE = 0, ALIGN(4)
#else
.const_cla : LOAD = FLASH_BANK0_SEC2_RSVD,
RUN = RAMLS1_7,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
PAGE = 0, ALIGN(4)
#endif
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
