CMD file error when copying Compiler Sections From Flash to RAM on F28377S Device

mao peng

Intellectual 490 points

I want to copy my code from flash into ram.

Question1:

My cmd file have one error.

The meaasge and my CMD file are as following.

It seems some problem on ".text" section.

How to modify it?

----------------------------------------------------------------------------------------------------------------------------------------

"../Load_Flash_Run_Ram/F2837xS_FlahLink_AllCodeInRAM_my.cmd", line 144: error #10099-D:
program will not fit into available memory. run placement with
alignment/blocking fails for section ".text" size 0xf20 page 0. Available
memory ranges:
RAMM0 size: 0x2de unused: 0x74 max hole: 0x72
RAMD0 size: 0x800 unused: 0x800 max hole: 0x800
RAMLS0 size: 0x800 unused: 0x800 max hole: 0x800
RAMLS1 size: 0x800 unused: 0x800 max hole: 0x800
RAMLS2 size: 0x800 unused: 0x800 max hole: 0x800
RAMLS3 size: 0x800 unused: 0x800 max hole: 0x800
RAMLS4 size: 0x800 unused: 0x800 max hole: 0x800
error #10010: errors encountered during linking; "F28377S.out" not built

-------------------------------------------------------------------------------------------------------------------------------------------------

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000122, length = 0x0002DE
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x000800
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RESET           	: origin = 0x3FFFC0, length = 0x000002

   RAMGS15   		: origin = 0x01B000, length = 0x001000
   /* Flash sectors Bank0  */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */

   /* Flash sectors Bank1  */
   /*Only one bank can be programmed or erased at a time. 
     The Flash API can be executed from RAM, or since there are two Flash banks for one CPU,
	 the Flash API code can be executed from one bank to erase/program the other bank. 
     Note that an extra wait state is automatically added when code is fetched or data is read from Bank 1, even for prefetched data. */
	 
   /*Note that Flash API execution is interruptible. However, there
     should not be any read/fetch access from the Flash bank on which an erase/program operation is in
     progress. For dual bank devices, Flash API can be executed from one Flash bank to perform
     erase/program operations on the other Flash bank. For single flash bank devices, Flash API must be
     executed from RAM and not from Flash   */
	 
   /*There are dedicated flash module controllers, FMC0 and FMC1 for Bank0 and Bank1, respectively. 
    The CPU interfaces with FMC0, which in turn interfaces with Bank0 and the shared pump to perform erase or
    program operations as well as to read data and execute code from the Bank0   */

   FLASHO           : origin = 0x0C0002, length = 0x001FFE	/* on-chip Flash */
   FLASHP           : origin = 0x0C2000, length = 0x002000	/* on-chip Flash */
   FLASHQ           : origin = 0x0C4000, length = 0x002000	/* on-chip Flash */
   FLASHR           : origin = 0x0C6000, length = 0x002000	/* on-chip Flash */
   FLASHS           : origin = 0x0C8000, length = 0x008000	/* on-chip Flash */
   FLASHT           : origin = 0x0D0000, length = 0x008000	/* on-chip Flash */
   FLASHU           : origin = 0x0D8000, length = 0x008000	/* on-chip Flash */
   FLASHV           : origin = 0x0E0000, length = 0x008000	/* on-chip Flash */
   FLASHW           : origin = 0x0E8000, length = 0x008000	/* on-chip Flash */
   FLASHX           : origin = 0x0F0000, length = 0x008000	/* on-chip Flash */
   FLASHY           : origin = 0x0F8000, length = 0x002000	/* on-chip Flash */
   FLASHZ           : origin = 0x0FA000, length = 0x002000	/* on-chip Flash */
   FLASHAA          : origin = 0x0FC000, length = 0x002000	/* on-chip Flash */
   FLASHAB          : origin = 0x0FE000, length = 0x002000	/* on-chip Flash */
   
   
PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   RAMGS11     : origin = 0x017000, length = 0x001000
   
   /*Available only on F28379S, F28377S, and F28375S	*/
   RAMGS12   : origin = 0x018000, length = 0x001000
   RAMGS13   : origin = 0x019000, length = 0x001000
   RAMGS14   : origin = 0x01A000, length = 0x001000


   /*            CAN X Message RAM	*/
   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
}

SECTIONS
{
    codestart           :  > BEGIN,    		   	PAGE = 0, ALIGN(4)
    wddisable	        :  >>FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN    PAGE = 0, ALIGN(4)
    copysections        :  >>FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN    PAGE = 0, ALIGN(4)

   .reset              :  > RESET,     			PAGE = 0, TYPE = DSECT /* not used, */
   .stack              :  > RAMM1,              PAGE = 1
   .ebss               :  >>RAMD1 | RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
   .esysmem            :  >>RAMD1 | RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1

   /* Initalized sections go in Flash */
   .cinit		:		LOAD = FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN    PAGE = 0, ALIGN(4)        /* can be ROM */ 
                		RUN = RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, 		PAGE = 0       /* must be CSM secured RAM */
                		LOAD_START(_cinit_loadstart),
                		RUN_START(_cinit_runstart),
                		SIZE(_cinit_size)
    
   .const		:   	LOAD = FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN    PAGE = 0, ALIGN(4)        /* can be ROM */ 
                		RUN = RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, 		PAGE = 0        /* must be CSM secured RAM */
                		LOAD_START(_const_loadstart),
                		RUN_START(_const_runstart),
                		SIZE(_const_size)
   
    .econst		:   	LOAD = FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN    PAGE = 0, ALIGN(4)        /* can be ROM */ 
                		RUN = RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, 		PAGE = 0        /* must be CSM secured RAM */
                		LOAD_START(_econst_loadstart),
               		    RUN_START(_econst_runstart),
                		SIZE(_econst_size)
    
    .pinit		:   	LOAD = FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN    PAGE = 0, ALIGN(4)        /* can be ROM */ 
                		RUN = RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, 		PAGE = 0        /* must be CSM secured RAM */
                		LOAD_START(_pinit_loadstart),
                		RUN_START(_pinit_runstart),
                		SIZE(_pinit_size)		
				
				
    .switch		:   	LOAD = FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN    PAGE = 0, ALIGN(4)        /* can be ROM */ 
                		RUN = RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, 		PAGE = 0        /* must be CSM secured RAM */
                		LOAD_START(_switch_loadstart),
                		RUN_START(_switch_runstart),
                		SIZE(_switch_size)


    .text		:   	LOAD = FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN    PAGE = 0, ALIGN(4)       /* can be ROM */ 
                		RUN = RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, 		PAGE = 0        /* must be CSM secured RAM */
                		LOAD_START(_text_loadstart),
                		RUN_START(_text_runstart),
                		SIZE(_text_size)
  
/*
#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} LOAD = FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN,
                         RUN = RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)
   #endif
#endif
*/

   ramgs0           : > RAMGS0,    PAGE = 1
   ramgs1           : > RAMGS1,    PAGE = 1

   /* The following section definitions are for SDFM examples */
   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111				
   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222				
   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333				
   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444				
   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333			
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/



Question2:

What is this about ".TI.ramfunc " section?  Just like "ramfuncs" section?

How can I modify ".TI.ramfunc " section in my CMD file when copying Compiler Sections From Flash to RAM?

In the above my CMD file, it 's just as code comment with no use.

over 9 years ago

0 Gautam Iyer over 9 years ago

Guru 192875 points

Hi,

Did you check with the "Memory Allocation" tool ? Also, check this pdf: www.ti.com/.../spraau8.pdf
It seems like your .text section is overflowing.

Regards,
Gautam

0 mao peng over 9 years ago in reply to Gautam Iyer

Intellectual 490 points

Hello Gautam,
Thanks for your reply.
I have read "spraau8.pdf " as well as example provided in this document yet.

I think I got the answer.
Try to modify code lik following can remove this error.
-------------------------------------------------------
.text : LOAD >> FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN PAGE = 0, ALIGN(4) /* can be ROM */
RUN >> RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, PAGE = 0 /* must be CSM secured RAM */
LOAD_START(_text_loadstart),
RUN_START(_text_runstart),
SIZE(_text_size)
-------------------------------------------------------

Repace "LOAD =" and "RUN =" with "LOAD >>" and "RUN >>", respectively.
Then, compiling is successful.
But I don't know why.

0 mao peng over 9 years ago in reply to mao peng

Intellectual 490 points

Another question,
What is this about ".TI.ramfunc " section? Just like "ramfuncs" section?
How can I modify ".TI.ramfunc " section in my CMD file when copying Compiler Sections From Flash to RAM?
In the following my CMD file, it 's just as code comment with no use.

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000122, length = 0x0002DE
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x000800
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RESET           	: origin = 0x3FFFC0, length = 0x000002


   /* Flash sectors Bank0  */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */

   /* Flash sectors Bank1  */
   /*Only one bank can be programmed or erased at a time. 
     The Flash API can be executed from RAM, or since there are two Flash banks for one CPU,
	 the Flash API code can be executed from one bank to erase/program the other bank. 
     Note that an extra wait state is automatically added when code is fetched or data is read from Bank 1, even for prefetched data. */
	 
   /*Note that Flash API execution is interruptible. However, there
     should not be any read/fetch access from the Flash bank on which an erase/program operation is in
     progress. For dual bank devices, Flash API can be executed from one Flash bank to perform
     erase/program operations on the other Flash bank. For single flash bank devices, Flash API must be
     executed from RAM and not from Flash   */
	 
   /*There are dedicated flash module controllers, FMC0 and FMC1 for Bank0 and Bank1, respectively. 
    The CPU interfaces with FMC0, which in turn interfaces with Bank0 and the shared pump to perform erase or
    program operations as well as to read data and execute code from the Bank0   */

   FLASHO           : origin = 0x0C0002, length = 0x001FFE	/* on-chip Flash */
   FLASHP           : origin = 0x0C2000, length = 0x002000	/* on-chip Flash */
   FLASHQ           : origin = 0x0C4000, length = 0x002000	/* on-chip Flash */
   FLASHR           : origin = 0x0C6000, length = 0x002000	/* on-chip Flash */
   FLASHS           : origin = 0x0C8000, length = 0x008000	/* on-chip Flash */
   FLASHT           : origin = 0x0D0000, length = 0x008000	/* on-chip Flash */
   FLASHU           : origin = 0x0D8000, length = 0x008000	/* on-chip Flash */
   FLASHV           : origin = 0x0E0000, length = 0x008000	/* on-chip Flash */
   FLASHW           : origin = 0x0E8000, length = 0x008000	/* on-chip Flash */
   FLASHX           : origin = 0x0F0000, length = 0x008000	/* on-chip Flash */
   FLASHY           : origin = 0x0F8000, length = 0x002000	/* on-chip Flash */
   FLASHZ           : origin = 0x0FA000, length = 0x002000	/* on-chip Flash */
   FLASHAA          : origin = 0x0FC000, length = 0x002000	/* on-chip Flash */
   FLASHAB          : origin = 0x0FE000, length = 0x002000	/* on-chip Flash */
   
   
PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   RAMGS11     : origin = 0x017000, length = 0x001000
   
   /*Available only on F28379S, F28377S, and F28375S	*/
   RAMGS12   : origin = 0x018000, length = 0x001000
   RAMGS13   : origin = 0x019000, length = 0x001000
   RAMGS14   : origin = 0x01A000, length = 0x001000
   RAMGS15   : origin = 0x01B000, length = 0x001000


   /*            CAN X Message RAM	*/
   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
}

SECTIONS
{
    codestart           :  > BEGIN,    		   	PAGE = 0, ALIGN(4)
    wddisable	        :  >>FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN    PAGE = 0, ALIGN(4)
    copysections        :  >>FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN    PAGE = 0, ALIGN(4)

   .reset              :  > RESET,     			PAGE = 0, TYPE = DSECT /* not used, */
   .stack              :  > RAMM1,              PAGE = 1
   .ebss               :  >>RAMD1 | RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
   .esysmem            :  >>RAMD1 | RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1

   /* Initalized sections go in Flash */
.cinit		:LOAD > FLASHA | FLASHB,       PAGE = 0, ALIGN(4),				/* can be ROM */
                 RUN  > RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, 	PAGE = 0,    		/* must be CSM secured RAM */
                 LOAD_START(_cinit_loadstart),
                 RUN_START(_cinit_runstart),
                 SIZE(_cinit_size)
                		
    
.const		:LOAD >> FLASHA | FLASHB,       PAGE = 0, ALIGN(4),/* can be ROM */
                 RUN >> RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, PAGE = 0,		 /* must be CSM secured RAM */
                 LOAD_START(_const_loadstart),
                 RUN_START(_const_runstart),
                 SIZE(_const_size)


.econst		:LOAD >> FLASHA | FLASHB,       PAGE = 0, ALIGN(4), /* can be ROM */
                 RUN >> RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, PAGE = 0,		/* must be CSM secured RAM */
                 LOAD_START(_econst_loadstart),
               	 RUN_START(_econst_runstart),
                 SIZE(_econst_size)

    
.pinit		:LOAD > FLASHA | FLASHB,   PAGE = 0, ALIGN(4),     /* can be ROM */
                 RUN  > RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, PAGE = 0, /* must be CSM secured RAM */
                 LOAD_START(_pinit_loadstart),
                 RUN_START(_pinit_runstart),
                 SIZE(_pinit_size)
				
				
.switch		:LOAD >> FLASHA | FLASHB,  PAGE = 0, ALIGN(4),      /* can be ROM */
                 RUN >> RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4, PAGE = 0,		      /* must be CSM secured RAM */
                 LOAD_START(_switch_loadstart),
                 RUN_START(_switch_runstart),
                 SIZE(_switch_size)


.text	:LOAD>> FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN,  PAGE = 0, ALIGN(4),        
         RUN >> RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4,   PAGE = 0,   /* must be CSM secured RAM */
         LOAD_START(_text_loadstart),
         RUN_START(_text_runstart),
         SIZE(_text_size)
  
/*
#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} LOAD = FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI| FLASHJ| FLASHK| FLASHL| FLASHM| FLASHN,
                         RUN = RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3 |RAMLS4,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)
   #endif
#endif
*/

   ramgs0           : > RAMGS0,    PAGE = 1
   ramgs1           : > RAMGS1,    PAGE = 1

   /* The following section definitions are for SDFM examples */
   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111				
   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222				
   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333				
   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444				
   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333			
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

0 Gautam Iyer over 9 years ago in reply to mao peng

Guru 192875 points

Repace "LOAD =" and "RUN =" with "LOAD >>" and "RUN >>", respectively.
Then, compiling is successful.
But I don't know why.

I somehow missed that! You're right and the link below will explain why.

processors.wiki.ti.com/.../C28x_Compiler_-_Understanding_Linking

0 mao peng over 9 years ago in reply to Gautam Iyer

Intellectual 490 points

Thanks Gautam,
I see "C28x Compiler - Understanding Linking",
very nice answer.

0 Gautam Iyer over 9 years ago in reply to mao peng

Guru 192875 points

You're Welcome!

Goodluck & Regards,
Gautam

C2000™︎ microcontrollers

C2000 microcontrollers forum

CMD file error when copying Compiler Sections From Flash to RAM on F28377S Device