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Help! An issue about reading and writting status registers( i.e. ST0 and ST1).

xianglin hwang
Prodigy 30 points
Other Parts Discussed in Thread: TMS320F28377S

I'm migrating an embeded OS to TMS320F28377s and I need to write two functions for entering and exiting critical zone. When entering critical zone, the function needs to read and return the values of ST0 and ST1 and then disable all maskable interrupts; When exiting critical zone, the function needs to load the values given by a caller to ST0 and ST1 and then enable all maskable interrupts. The problem is that I can't find any instruction that can read or write ST0 and ST1 directly. In fact, I have an idea shown as follows, but I am not sure if it is a good solution. Is there any better suggestion?

_OS_ENTER_CRITICAL:
        PUSH        ST0
        PUSH        ST1
        POP           ACC
        DINT
        LRETR

_OS_EXIT_CRITICAL:
        PUSH        ACC
        POP          ST1
        POP          ST0
        EINT
        LRETR

  • 0
    TI__Guru 53105 points
    Hello,

    I think this code looks fine. I don't have any better suggestion. You are correct that the architecture limits ST0 and ST1 to pushing and popping instead of doing a direct MOV.

    Whitney
  • 0 in reply to Whitney Dewey
    Prodigy 30 points

    Thank you, Whitney! With your reply, I am clear that there is no instruction directly storing or loading ST0 and ST1 and my idea is OK.

    Now, there is another problem that confuse me. Look at the assembly code below, I wonder what does "*AR1" mean. I can't find any description about the addressing mode syntax like "*ARn" in C28X instruction set reference guide, but the assembler treat it as a legal instruction. The most similar expression is "MOV      AL,*XAR1", which is the same encoding as “MOV        AL,*+XAR1[0]”. Can you tell me what dose "*ARn" stands for and what will the CPU do when it gets the instruction below?

    mov        AL, *AR1

  • 0 in reply to xianglin hwang
    TI__Guru 53105 points
    ARn is used to indicate the lower half of the XARn register. So the instruction you've given as an example would move the value pointed to by the lower 16-bits of XAR1 to AL.

    Whitney
  • 0 in reply to Whitney Dewey
    Prodigy 30 points

    I get it. Your reply is helpful! BTW, is "*ARn" only able to access the lower 64K of data space?