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TMS320F28034: SCI generates unexpected transmit (TX) interrupts when using FIFO enhancements

Edward Jakob54
Prodigy 60 points
Part Number: TMS320F28034

During initialization, my application configures the TMS320F28034's SCI to operate in FIFO enhanced mode with interrupts.  Even before any data is transmitted by the SCI, the SCI's TX interrupt is generated whenever the TX FIFO enhancements are enabled.

The following instruction seems to be causing the problem:

SciaRegs.SCIFFTX.bit.SCIFFENA = 1;

Resetting the SCI channels (see instructions below) momentarily remedies the situation

SciaRegs.SCIFFTX.bit.SCIRST = 0;

SciaRegs.SCIFFTX.bit.SCIRST = 1;

Resetting the SCI's TX FIFOs (see instructions below) momentarily remedies the situation

SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 0;

SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 1;

But the following instruction, the one that clears the FIFO TX interrupt flag

SciaRegs.SCIFFTX.bit.TXFFINTCLR = 1;

Does NOT do anything to clear the unwanted interrupt flag.

Does anyone have any suggestions?  I've seen where people use some state machine logic, but this seems like a very cumbersome solution.

  • 0
    TI__Mastermind 42195 points

     Edward,

    When using the FIFO enhancements the interrupt that you are receiving can be thought of "the SCI is requesting more messages to be put in it's FIFO". This interrupt occurs anytime TXFFST<= TXFFIL. You are correct, you can clear the interrupt with "SciaRegs.SCIFFTX.bit.TXFFINTCLR = 1;", but it will be immeaditly reset if TXFFST is still less than or equal to TXFFIL. I would encourage you to read the SCI Reference Guide, it describes all of these bits/ registers you are using.

    Regards,
    Cody