Fifo SCI Transmit Interrupt in TMS320F28035

Sunil,

SCIFFENA is not FIFO interrupt enable bit.  It is used to enable/disable SCI transmit FIFO and SCI receive FIFO.  In order to use FIFOs, this bit has to be set. 

RXFFIENA (bit 5 of SCIFFRX register) is receive FIFO interrupt enable bit.  TXFFIENA (bit 5 of SCIFFTX register) is transmit FIFO interrupt enable bit.  I think you did not enable TXFFIENA and hence transmit FIFO interrupt is not working.

Look at "Figure 10. SCI FIFO Interrupt Flags and Enable Logic" in SCI reference guide for more clarity

Regards,

Vamsi

Thank you Vamsi,

Sorry that was a typo on my part. I am actually using the bits you mentioned in following lines as you can see.

void scia_fifo_init()
{
   SciaRegs.SCICCR.all =0x0007;   // 1 stop bit,  No loopback
                                  // No parity,8 char bits,
                                  // async mode, idle-line protocol
   SciaRegs.SCICTL1.all =0x0003;  // enable TX, RX, internal SCICLK,
                                  // Disable RX ERR, SLEEP, TXWAKE

   SciaRegs.SCIFFTX.bit.SCIFFENA = 1;    // enable FIFO mode (strange place to keep this bit here!)
   SciaRegs.SCIFFTX.bit.SCIRST =1;        // reset FIFO just in case.   
   //SciaRegs.SCICTL2.bit.TXINTENA =1;    // enable tx interrupt
   SciaRegs.SCIFFTX.bit.TXFFIENA = 1;    //enable Fifo tx interrupt
   SciaRegs.SCIHBAUD = 0x0000;
   SciaRegs.SCILBAUD = SCI_PRD;
   SciaRegs.SCIFFTX.bit.TXFFIL = 0;        //Tx interrupt when empty
   SciaRegs.SCIFFRX.bit.RXFFIL = FifoSize;        //Rx interrupt when rx is filled upto 4 bytes.
   SciaRegs.SCIFFRX.bit.RXFFIENA = 1;    //enable rx interrupt
   SciaRegs.SCIFFCT.bit.FFTXDLY = 0;   //no delay between words transmitted.
   SciaRegs.SCICTL1.all =0x0023;     // Relinquish SCI from Reset
   SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
   SciaRegs.SCIFFRX.bit.RXFIFORESET=1;

}

Thank you Once again Vamsi,

Solved !

Order matters. Example has main function with following instructions in order. (comments removed for brevity.)

   InitSysCtrl();

   InitSciGpio();

   DINT;

   InitPieCtrl();

   IER = 0x0000;

   IFR = 0x0000;

InitPieVectTable();

EALLOW;

   PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
   PieVectTable.SCITXINTA = &sciaTxFifoIsr;

   EDIS;

   scia_fifo_init();  // Init SCI-A

   for(i = 0; i<2; i++)
   {
      sdataA[i] = i;
   }

   rdata_pointA = sdataA[0];

   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
   PieCtrlRegs.PIEIER9.bit.INTx1=1;     // PIE Group 9, INT1
   PieCtrlRegs.PIEIER9.bit.INTx2=1;     // PIE Group 9, INT2
   IER = 0x100; // Enable CPU INT
   EINT;

In my code the    scia_fifo_init();   was with    InitSciGpio(); as follows.

  InitSysCtrl();

   InitSciGpio();

   scia_fifo_init();

   DINT;

   InitPieCtrl();

I think that it was causing premature TX interrupt. It needs to be in the DINT-EINT shell. Or you can explain it better.

sunil

Sunil, would you post detailed solution/code on this topic? I tried to follow your posting and still unable to make RX interrupt work.

I am also using F28035 for SCI, connecting to a PC via RS232. I tried to echoback to verify my hardware config. it worked fine. When I tried loopback_interrupt example (only disable loopback bit, SciaRegs.SCICCR.bit.LOOPBKENA =0, and injecting random text from PC and watching registers/rdata), TX interrupt worked, but not RX. interrupt never fired.

if you prefer, you might zip your working example project  and send to me privately. (jizhong_wang@gl-electric.com)

Thanks a lot

Jizhong

I have figured this out.

I need to disable FIFO for Tx/Rx interrupts working reliably for SCI communication.

Jizhong