LAUNCHXL-F28377S: What is the __interrupt void cpu_timer0_isr(void)?

Hi Takano-san,

That's the CPU Timer ISR i.e. if you configure the timer to 1ms, the ISR would be served every 1ms according to Interrupt Vector Table priority.

Regards,
Gautam

Hi,

Is an Interrupt Service Routine (ISR) is a routine which is executed after the interrupt belonging to an interrupt vector?
So, in that example, CpuTimer0.InterruptCount++; is the main routine, and what is purpose of PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;?

Best,
Takano

Takano said:

Is an Interrupt Service Routine (ISR) is a routine which is executed after the interrupt belonging to an interrupt vector?

Yup

Takano said:

So, in that example, CpuTimer0.InterruptCount++; is the main routine, and what is purpose of PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;?

If you look at the interrupt vector table you'll find that CPU_Timer belongs to Group1 interrupts.

Hi,

You mean that this code is the one?
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
So, does this mean that vector no. 7 is assigned to this interrupt by "1" flag assertion?

Regards,
Takano

Hi,

While configuring a peripheral interrupt, one needs to enable the Interrupt at various levels.

First at peripheral level,

CpuTimer0Regs.TCR.bit.TIE = 1;  // Enable Timer 0 interrupt at peripheral level.

Second at Peripheral Interrupt Expansion(PIE) level,

PieCtrlRegs.PIEIER1.bit.INTx7 = 1; // Enable Timer 0 interrupt at PIE level.

Third at CPU level,

IER |= M_INT1; // Enable Timer 0 interrupt at CPU level.

And finally one has to enable interrupts at global level,

EINT;

If you look at the following figure, you can see that the processor supports only 16 interrupts in addition to an NMI. ePIE is used to map the large number of interrupts from various peripherals to the 12 interrupt lines (INT1 through INT12) going to the CPU.

If you read through the PIE channel mapping, it is clear that Timer 0 is connected at INT1 line to processor. The INT1 line in PIE block can further be mux'ed/connected to 16 interrupt sources as shown in row 1 of following figure. Among which Timer 0 stands at position 7. Hence, Timer 0 is connected at PIEIER1.INTx7, and is enabled by setting the corresponding bit as can be seen in the example code.

Once you've configured your interrupts properly and an interrupt is serviced, you need to acknowledge the same to accept further interrupts from Group/Row 1 of PIE block. The following line does that,

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt from PIE block Row 1 (Interrupt has been serviced)

as Timer 0 belongs to Group/Row 1 of PIE block (see above figure highlight).

I would suggest you go through "2.4 Peripheral Interrupts" section in the F28377S Technical Reference Manual (Rev. D) on page 84.

That would clear up your doubts.

Regards,

S.A Sadiq

Hi, 

Thank you very much for your replying, it is very understandable for me.

After all, in case of use of timer-0, in order to use the timer interrupt, we must set up 4-level path as you told me, right?

Again, thank you very much. I will reply question if I have an issue when I try to do it.

Best,

Takano

Hi,

1. Correction :

As per "TMS320C28x CPU and Instruction Set Reference Guide"  (spru430f), the C28x CPU supports a total of 32 interrupts not 16 interrupts out of which 12 (INT1 through INT12) are connected to ePIE block. Refer page 54, Table 3-1.

2. Yes Takano, All peripheral interrupts routed through ePIE will usually go through the 4-level path. So even for Timer 0 it will be the same.

The other 20 (32 - 12) interrupts which are not connected to ePIE cannot be enabled at the PIE level as they are directly connected to the CPU.

3. Note that for each interrupt you've enabled, you also specify the vector address in the PIEVECTTABLE register like,

PieVectTable.TIMER0_INT = &cpu_timer0_isr;  // Execute the function 'cpu_timer0_isr()' when Timer 0 interrupt occurs. 

The vector address has to be specified in the PIEVECTTABLE register for all enabled INTs irrespective of whether they are connected directly to CPU or connected via the ePIE block..

Regards,

S.A Sadiq