Hi Champs,
My customer is designing digital power product using F28035. Now they found MCU would reset by external interference. They found PLL would be corrupted by interference, looks CLOCKFAIL occured.
XTAL clock is 20MHz, and CPU clock is set to 60MHz, while XCLKOUT is used to monitor the SYSCLKOUT.
The clock initialization code is as follows.
void InitSysCtrl(void)
{
DisableDog();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // Enable ADC peripheral clock
(*Device_cal)();
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0; // Return ADC clock to original state
EDIS;
XtalOscSel();
InitPll(6,2);//(OSCCLK * 6)/2=20M*6/2=60M
InitPeripheralClocks();
}
void XtalOscSel (void) {
EALLOW;
SysCtrlRegs.CLKCTL.bit.XTALOSCOFF = 0; // Turn on XTALOSC
SysCtrlRegs.CLKCTL.bit.XCLKINOFF = 1; // Turn off XCLKIN
SysCtrlRegs.CLKCTL.bit.OSCCLKSRC2SEL = 0; // Switch to external clock
SysCtrlRegs.CLKCTL.bit.OSCCLKSRCSEL = 1; // Switch from INTOSC1 to INTOSC2/ext clk
SysCtrlRegs.CLKCTL.bit.WDCLKSRCSEL = 1; // Switch Watchdog Clk Src to external clock
SysCtrlRegs.CLKCTL.bit.INTOSC2OFF = 1; // Turn off INTOSC2
SysCtrlRegs.CLKCTL.bit.INTOSC1OFF = 1; // Turn off INTOSC1
EDIS;
}
void InitPll(Uint16 val, Uint16 divsel)
{
volatile Uint16 iVol;
// Make sure the PLL is not running in limp mode
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
{
EALLOW;
// OSCCLKSRC1 failure detected. PLL running in limp mode.
// Re-enable missing clock logic.
SysCtrlRegs.PLLSTS.bit.MCLKCLR = 1;
EDIS;
// Replace this line with a call to an appropriate
// SystemShutdown(); function.
__asm(" ESTOP0"); // Uncomment for debugging purposes 卡死在这个位置了！！！！！
}
......
}
The watchdog code:
SysCtrlRegs.WDCR = 0x002A;
WDCLK = OSCCLK/512/2 = 20M/512/2=19.531kHz=51.2us；
Watchdog overflow time = 51.2us*256=13.1ms
If CLOCKFAIL occured, NMIWD will reset the device. In there code, they set NMICFG[CLOCKFAIL] and NMIWDPRD, NMIRESETSEL = 1. You can find the scope captures as follows. BLUE waveform is PWM output, YELLOW wavefrom is XCLKOUT.
1. NMIRESETSEL = 1，NMIWDPRD=3000. when CLOCKFAIL occurred, PWM frequency was changed from 100KHz to 33KHz, and XCLKOUT from 60MHz to 20MHz, and the time is about 150us.
After reset, SYSCLKOUT is 60Mhz lasting 50us.
After that, NMIRESETSEL = 1，NMIWDPRD=6000,
Would you kindly help to analyze why this failure happened? After reset, why SYSCLKOUT changes from 60Mhz to 20MHz? Thanks.
BR,
Young.
