Compiler/TMS320F28377S: CLA is not working in TMS320F28377S

Sreedhar Kaduru

Prodigy 120 points

Part Number: TMS320F28377S
Other Parts Discussed in Thread: C2000WARE

Tool/software: TI C/C++ Compiler

CLA problem:

1) I have created a project with following cmd files.

2) I have taken .c , .h and .cla files from example code of cla_divide.

3) I have successfully build Project work space .

4) I have connected LaunchPad to PC, and tried to run in debug mode..

5) But debugger is stopped at Cla1ForceTask1andWait() in cla_divide_cpu01.c

CCS compiler version is 16.9.1.LTS

MEMORY
{
PAGE 0: /* Program Memory */

PAGE 1: /* Data Memory */

ADCA_RESULT : origin = 0x000B00, length = 0x000020
ADCB_RESULT : origin = 0x000B20, length = 0x000020
ADCC_RESULT : origin = 0x000B40, length = 0x000020
ADCD_RESULT : origin = 0x000B60, length = 0x000020

ADCA : origin = 0x007400, length = 0x000080
ADCB : origin = 0x007480, length = 0x000080
ADCC : origin = 0x007500, length = 0x000080
ADCD : origin = 0x007580, length = 0x000080

ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080

CANA : origin = 0x048000, length = 0x000800
CANB : origin = 0x04A000, length = 0x000800

CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */

CLB_XBAR : origin = 0x007A40, length = 0x000040

CMPSS1 : origin = 0x005C80, length = 0x000020
CMPSS2 : origin = 0x005CA0, length = 0x000020
CMPSS3 : origin = 0x005CC0, length = 0x000020
CMPSS4 : origin = 0x005CE0, length = 0x000020
CMPSS5 : origin = 0x005D00, length = 0x000020
CMPSS6 : origin = 0x005D20, length = 0x000020
CMPSS7 : origin = 0x005D40, length = 0x000020
CMPSS8 : origin = 0x005D60, length = 0x000020

CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */
CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */

DACA : origin = 0x005C00, length = 0x000010
DACB : origin = 0x005C10, length = 0x000010
DACC : origin = 0x005C20, length = 0x000010

DMA : origin = 0x001000, length = 0x000200
DMACLASRCSEL : origin = 0x007980, length = 0x000040

ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */
ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */
ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */
ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */
ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */
ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */

EMIF1 : origin = 0x047000, length = 0x000800
EMIF2 : origin = 0x047800, length = 0x000800

EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */
EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */
EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */

EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */
EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */
EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */
EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */
EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */
EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */
EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */
EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */
EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */
EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */
EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */
EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */

EPWM_XBAR : origin = 0x007A00, length = 0x000040

FLASH0_CTRL : origin = 0x05F800, length = 0x000300
FLASH0_ECC : origin = 0x05FB00, length = 0x000040
FLASH1_CTRL : origin = 0x05FC00, length = 0x000300
FLASH1_ECC : origin = 0x05FF00, length = 0x000040

GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */
GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */

OUTPUT_XBAR : origin = 0x007A80, length = 0x000040
I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */
I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */

FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002

ROMPREFETCH : origin = 0x05E608, length = 0x000002

MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */
EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */
EMIF2CONFIG : origin = 0x05F4A0, length = 0x000020 /* Emif-2 Config registers */
ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */
MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */
ROMWAITSTATE : origin = 0x05F540, length = 0x000002 /* ROM Config registers */

MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */
MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */

NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */

PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */
SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */
SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */
SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */
SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */

SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */
SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */

SPIA : origin = 0x006100, length = 0x000010
SPIB : origin = 0x006110, length = 0x000010
*** : origin = 0x006120, length = 0x000010
SPID : origin = 0x006130, length = 0x000010

UPP : origin = 0x006200, length = 0x000100 /* uPP registers */

DEV_CFG : origin = 0x05D000, length = 0x000180
CLK_CFG : origin = 0x05D200, length = 0x000100
CPU_SYS : origin = 0x05D300, length = 0x000100

INPUT_XBAR : origin = 0x007900, length = 0x000020
XBAR : origin = 0x007920, length = 0x000020
SYNC_SOC : origin = 0x007940, length = 0x000010
WD : origin = 0x007000, length = 0x000040

XINT : origin = 0x007070, length = 0x000010

DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */
DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */
DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */

DCSM_Z1_OTP : origin = 0x078000, length = 0x000020 /* Part of Z1 OTP. LinkPointer/JTAG lock/ Boot Mode */
DCSM_Z2_OTP : origin = 0x078200, length = 0x000020 /* Part of Z2 OTP. LinkPointer/JTAG lock */
}

SECTIONS
{
/*** PIE Vect Table and Boot ROM Variables Structures ***/
UNION run = PIE_VECT, PAGE = 1
{
PieVectTableFile
GROUP
{
EmuKeyVar
EmuBModeVar
FlashCallbackVar
FlashScalingVar
}
}

AdcaResultFile : > ADCA_RESULT, PAGE = 1
AdcbResultFile : > ADCB_RESULT, PAGE = 1
AdccResultFile : > ADCC_RESULT, PAGE = 1
AdcdResultFile : > ADCD_RESULT, PAGE = 1

AdcaRegsFile : > ADCA, PAGE = 1
AdcbRegsFile : > ADCB, PAGE = 1
AdccRegsFile : > ADCC, PAGE = 1
AdcdRegsFile : > ADCD, PAGE = 1

AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1

CanaRegsFile : > CANA, PAGE = 1
CanbRegsFile : > CANB, PAGE = 1

Cla1RegsFile : > CLA1, PAGE = 1
Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT

ClbXbarRegsFile : > CLB_XBAR PAGE = 1

Cmpss1RegsFile : > CMPSS1, PAGE = 1
Cmpss2RegsFile : > CMPSS2, PAGE = 1
Cmpss3RegsFile : > CMPSS3, PAGE = 1
Cmpss4RegsFile : > CMPSS4, PAGE = 1
Cmpss5RegsFile : > CMPSS5, PAGE = 1
Cmpss6RegsFile : > CMPSS6, PAGE = 1
Cmpss7RegsFile : > CMPSS7, PAGE = 1
Cmpss8RegsFile : > CMPSS8, PAGE = 1

CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1

DacaRegsFile : > DACA PAGE = 1
DacbRegsFile : > DACB PAGE = 1
DaccRegsFile : > DACC PAGE = 1

DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1
DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1
DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1

/*** Warning: Only remove "Type = NOLOAD" to program OTP Locations ***/
DcsmZ1OtpFile : > DCSM_Z1_OTP, PAGE = 1, type = NOLOAD
DcsmZ2OtpFile : > DCSM_Z2_OTP, PAGE = 1, type = NOLOAD

DmaRegsFile : > DMA PAGE = 1
DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1

ECap1RegsFile : > ECAP1, PAGE = 1
ECap2RegsFile : > ECAP2, PAGE = 1
ECap3RegsFile : > ECAP3, PAGE = 1
ECap4RegsFile : > ECAP4, PAGE = 1
ECap5RegsFile : > ECAP5, PAGE = 1
ECap6RegsFile : > ECAP6, PAGE = 1

Emif1RegsFile : > EMIF1 PAGE = 1
Emif2RegsFile : > EMIF2 PAGE = 1

EPwm1RegsFile : > EPWM1, PAGE = 1
EPwm2RegsFile : > EPWM2, PAGE = 1
EPwm3RegsFile : > EPWM3, PAGE = 1
EPwm4RegsFile : > EPWM4, PAGE = 1
EPwm5RegsFile : > EPWM5, PAGE = 1
EPwm6RegsFile : > EPWM6, PAGE = 1
EPwm7RegsFile : > EPWM7, PAGE = 1
EPwm8RegsFile : > EPWM8, PAGE = 1
EPwm9RegsFile : > EPWM9, PAGE = 1
EPwm10RegsFile : > EPWM10, PAGE = 1
EPwm11RegsFile : > EPWM11, PAGE = 1
EPwm12RegsFile : > EPWM12, PAGE = 1

EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1

EQep1RegsFile : > EQEP1, PAGE = 1
EQep2RegsFile : > EQEP2, PAGE = 1
EQep3RegsFile : > EQEP3, PAGE = 1

Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1
Flash0EccRegsFile : > FLASH0_ECC PAGE = 1
Flash1CtrlRegsFile : > FLASH1_CTRL PAGE = 1
Flash1EccRegsFile : > FLASH1_ECC PAGE = 1

GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1
GpioDataRegsFile : > GPIODAT, PAGE = 1

OutputXbarRegsFile : > OUTPUT_XBAR PAGE = 1
I2caRegsFile : > I2CA, PAGE = 1
I2cbRegsFile : > I2CB, PAGE = 1
InputXbarRegsFile : > INPUT_XBAR PAGE = 1
XbarRegsFile : > XBAR PAGE = 1

FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1

RomPrefetchRegsFile : > ROMPREFETCH, PAGE = 1
MemCfgRegsFile : > MEMCFG, PAGE = 1
Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1
Emif2ConfigRegsFile : > EMIF2CONFIG, PAGE = 1
AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1
MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1
RomWaitStateRegsFile : > ROMWAITSTATE, PAGE = 1

McbspaRegsFile : > MCBSPA, PAGE = 1
McbspbRegsFile : > MCBSPB, PAGE = 1

UppRegsFile : > UPP, PAGE = 1

NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1
PieCtrlRegsFile : > PIE_CTRL, PAGE = 1

SciaRegsFile : > SCIA, PAGE = 1
ScibRegsFile : > SCIB, PAGE = 1
ScicRegsFile : > SCIC, PAGE = 1
ScidRegsFile : > SCID, PAGE = 1

Sdfm1RegsFile : > SDFM1, PAGE = 1
Sdfm2RegsFile : > SDFM2, PAGE = 1

SpiaRegsFile : > SPIA, PAGE = 1
SpibRegsFile : > SPIB, PAGE = 1
SpicRegsFile : > ***, PAGE = 1
SpidRegsFile : > SPID, PAGE = 1

DevCfgRegsFile : > DEV_CFG, PAGE = 1
ClkCfgRegsFile : > CLK_CFG, PAGE = 1
CpuSysRegsFile : > CPU_SYS, PAGE = 1

SyncSocRegsFile : > SYNC_SOC, PAGE = 1

WdRegsFile : > WD, PAGE = 1

XintRegsFile : > XINT PAGE = 1
MemCfgRegs : > MEMCFG PAGE = 1

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C

MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to Flash" bootloader mode */

BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0

/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */

PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMD1 : origin = 0x00B800, length = 0x000800

RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800

RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */

CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}

SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHB PAGE = 0, ALIGN(4)
.pinit : > FLASHB, PAGE = 0, ALIGN(4)
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4)
codestart : > BEGIN PAGE = 0, ALIGN(4)

/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1
.esysmem : > RAMLS5 PAGE = 1

/* Initalized sections go in Flash */
.econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4)
.switch : > FLASHB PAGE = 0, ALIGN(4)

.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#else
ramfuncs : LOAD = FLASHD,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#endif
#endif

ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1

DLOG : > RAMGS5, PAGE = 1
SGENipcb : > RAMGS12, PAGE = 1
SGENipcbsrc : > RAMGS13, PAGE = 1

SINTBL : > RAMGS7, PAGE = 1

IQmath : > RAMLS1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD

/* CLA specific sections */
Cla1Prog : > RAMLS4_LS5, PAGE=0

CLADataLS0 : > RAMLS0, PAGE=1
CLADataLS1 : > RAMLS1, PAGE=1

Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1

/* The following section definitions are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333

#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS1, PAGE = 1

.scratchpad : > RAMLS1, PAGE = 1
.bss_cla : > RAMLS1, PAGE = 1
.const_cla : > RAMLS1, PAGE = 1
#endif //CLA_C
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

over 8 years ago

0 programmable solution over 8 years ago

Expert 1500 points

Hi,
If you look at Cla1ForceTask1andWait(), it is a macro.

#define Cla1ForceTask1andWait()asm(" IACK #0x0001"); \
asm(" RPT #3 || NOP"); \
while(Cla1Regs.MIRUN.bit.INT1 == 1);

I think if you replace the macro with the actual implied instructions, you'll find the CPU is hung on
while(Cla1Regs.MIRUN.bit.INT1 == 1);

0 Sal Pezzino over 8 years ago in reply to programmable solution

TI__Mastermind 32995 points

Agreed.

0 Sreedhar Kaduru over 8 years ago in reply to Sal Pezzino

Prodigy 120 points

yes, It is correct debugger is stopped at while(Cla1Regs.MIRUN.bit.INT1 == 1);
Could Please explain with an example it will more help to me.
Thanks for your support

0 Sreedhar Kaduru over 8 years ago in reply to programmable solution

Prodigy 120 points

Could you explain with an example .It will more help to me.
Thanks for your support.

0 Sreedhar Kaduru over 8 years ago in reply to Sreedhar Kaduru

Prodigy 120 points

0 programmable solution over 8 years ago in reply to Sreedhar Kaduru

Expert 1500 points

There is an example project that uses Cla1ForceTask1andWait() that you can import, build, run, and examine.

C:\ti\c2000\C2000Ware_1_00_01_00\device_support\f2837xs\examples\cpu1\cla_vminfloat

TI has a CLA FAQ page you may want to reference.

http://processors.wiki.ti.com/index.php/Control_Law_Accelerator_(C2000_CLA)_FAQ

0 Sal Pezzino over 8 years ago in reply to programmable solution

TI__Mastermind 32995 points

This may have to do with the memcpy of ramfuncs and CLA code/data. Are you using the latest C2000Ware? This should be fixed. Previously, the arguments for the memcpy were in the incorrect order.

sal

0 programmable solution over 8 years ago in reply to Sreedhar Kaduru

Expert 1500 points

Did the define CLA_C solve your problem.
If not
I was able to mimic the symptoms of your project with the cla_vminfloat_cpu01 project
in file vminfloat.cla, I added a few lines:

//Task 1 : Vector min
__interrupt void Cla1Task1 ( void )
{
__mdebugstop(); // added
min1 = vector1[4];
index1 = 4;

for(i = 3; i >= 0; i--)
{
if(vector1[i] < min1)
{
index1 = i;
min1 = vector1[i];
}
}
__mdebugstop(); // added
while(1); // added
}

the program now hangs at Cla1ForceTask1andWait(); in cla_vminfloat_cpu01.c

0 Sreedhar Kaduru over 8 years ago in reply to programmable solution

Prodigy 120 points

While debugging CLA code, I was not able to any data on memory location , I added debug screen shot .
I am suspecting cmd file problem. Could please review cmd file.
// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start#endif //CLA_CMEMORY{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080}SECTIONS{
/* Allocate program areas: */
.cinit : > FLASHB PAGE = 0, ALIGN(4)
.pinit : > FLASHB, PAGE = 0, ALIGN(4)
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4)
codestart : > BEGIN PAGE = 0, ALIGN(4)
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1
.esysmem : > RAMLS5 PAGE = 1
/* Initalized sections go in Flash */
.econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4)
.switch : > FLASHB PAGE = 0, ALIGN(4)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
/* CLA specific sections */ Cla1Prog : LOAD = FLASHD,
RUN = RAMLS4,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0, ALIGN(4) CLADataLS0 : > RAMLS0, PAGE=1
CLADataLS1 : > RAMLS1, PAGE=1
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
#ifdef __TI_COMPILER_VERSION__ #if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4) #else
ramfuncs : LOAD = FLASHD,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4) #endif#endif
/* The following section definitions are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
ramgs0 : > RAMGS6, PAGE = 1
ramgs1 : > RAMGS7, PAGE = 1
DLOG : > RAMGS5, PAGE = 1 SGENipcb : > RAMGS12, PAGE = 1
SGENipcbsrc : > RAMGS13, PAGE = 1
SINTBL : > RAMGS7, PAGE = 1
IQmath : > RAMLS1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD#ifdef CLA_C
/* CLA C compiler sections */ //
// Must be allocated to memory the CLA has write access to //
CLAscratch : { *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS1, PAGE = 1
.scratchpad : > RAMLS1, PAGE = 1
.bss_cla : > RAMLS1, PAGE = 1
.const_cla : LOAD = FLASHB, RUN = RAMLS1,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
PAGE = 1#endif //CLA_C}/*
//===========================================================================
// End of file.
//===========================================================================*/
MEMORY{ PAGE 0: /* Program Memory */ PAGE 1: /* Data Memory */
ADCA_RESULT : origin = 0x000B00, length = 0x000020
ADCB_RESULT : origin = 0x000B20, length = 0x000020
ADCC_RESULT : origin = 0x000B40, length = 0x000020
ADCD_RESULT : origin = 0x000B60, length = 0x000020
ADCA : origin = 0x007400, length = 0x000080
ADCB : origin = 0x007480, length = 0x000080
ADCC : origin = 0x007500, length = 0x000080
ADCD : origin = 0x007580, length = 0x000080
ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080
CANA : origin = 0x048000, length = 0x000800
CANB : origin = 0x04A000, length = 0x000800
CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */
CLB_XBAR : origin = 0x007A40, length = 0x000040
CMPSS1 : origin = 0x005C80, length = 0x000020
CMPSS2 : origin = 0x005CA0, length = 0x000020
CMPSS3 : origin = 0x005CC0, length = 0x000020
CMPSS4 : origin = 0x005CE0, length = 0x000020
CMPSS5 : origin = 0x005D00, length = 0x000020
CMPSS6 : origin = 0x005D20, length = 0x000020
CMPSS7 : origin = 0x005D40, length = 0x000020
CMPSS8 : origin = 0x005D60, length = 0x000020
CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */
CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */
DACA : origin = 0x005C00, length = 0x000010
DACB : origin = 0x005C10, length = 0x000010
DACC : origin = 0x005C20, length = 0x000010
DMA : origin = 0x001000, length = 0x000200
DMACLASRCSEL : origin = 0x007980, length = 0x000040
ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */
ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */
ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */
ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */
ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */
ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */
EMIF1 : origin = 0x047000, length = 0x000800
EMIF2 : origin = 0x047800, length = 0x000800
EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */
EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */
EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */
EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */
EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */
EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */
EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */
EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */
EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */
EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */
EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */
EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */
EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */
EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */
EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */
EPWM_XBAR : origin = 0x007A00, length = 0x000040
FLASH0_CTRL : origin = 0x05F800, length = 0x000300
FLASH0_ECC : origin = 0x05FB00, length = 0x000040
FLASH1_CTRL : origin = 0x05FC00, length = 0x000300
FLASH1_ECC : origin = 0x05FF00, length = 0x000040
GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */
GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */
OUTPUT_XBAR : origin = 0x007A80, length = 0x000040
I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */
I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */
FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002
ROMPREFETCH : origin = 0x05E608, length = 0x000002
MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */
EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */
EMIF2CONFIG : origin = 0x05F4A0, length = 0x000020 /* Emif-2 Config registers */
ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */
MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */
ROMWAITSTATE : origin = 0x05F540, length = 0x000002 /* ROM Config registers */
MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */
MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */
NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */
PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */
SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */
SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */
SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */
SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */
SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */
SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */
SPIA : origin = 0x006100, length = 0x000010
SPIB : origin = 0x006110, length = 0x000010
*** : origin = 0x006120, length = 0x000010
SPID : origin = 0x006130, length = 0x000010
UPP : origin = 0x006200, length = 0x000100 /* uPP registers */
DEV_CFG : origin = 0x05D000, length = 0x000180
CLK_CFG : origin = 0x05D200, length = 0x000100
CPU_SYS : origin = 0x05D300, length = 0x000100
INPUT_XBAR : origin = 0x007900, length = 0x000020
XBAR : origin = 0x007920, length = 0x000020
SYNC_SOC : origin = 0x007940, length = 0x000010
WD : origin = 0x007000, length = 0x000040
XINT : origin = 0x007070, length = 0x000010
DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */
DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */
DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */
DCSM_Z1_OTP : origin = 0x078000, length = 0x000020 /* Part of Z1 OTP. LinkPointer/JTAG lock/ Boot Mode */
DCSM_Z2_OTP : origin = 0x078200, length = 0x000020 /* Part of Z2 OTP. LinkPointer/JTAG lock */
}SECTIONS{/*** PIE Vect Table and Boot ROM Variables Structures ***/
UNION run = PIE_VECT, PAGE = 1 { PieVectTableFile GROUP {
EmuKeyVar EmuBModeVar FlashCallbackVar
FlashScalingVar } }
AdcaResultFile : > ADCA_RESULT, PAGE = 1
AdcbResultFile : > ADCB_RESULT, PAGE = 1
AdccResultFile : > ADCC_RESULT, PAGE = 1
AdcdResultFile : > ADCD_RESULT, PAGE = 1
AdcaRegsFile : > ADCA, PAGE = 1
AdcbRegsFile : > ADCB, PAGE = 1
AdccRegsFile : > ADCC, PAGE = 1
AdcdRegsFile : > ADCD, PAGE = 1
AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1
CanaRegsFile : > CANA, PAGE = 1
CanbRegsFile : > CANB, PAGE = 1
Cla1RegsFile : > CLA1, PAGE = 1
Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT
ClbXbarRegsFile : > CLB_XBAR PAGE = 1
Cmpss1RegsFile : > CMPSS1, PAGE = 1
Cmpss2RegsFile : > CMPSS2, PAGE = 1
Cmpss3RegsFile : > CMPSS3, PAGE = 1
Cmpss4RegsFile : > CMPSS4, PAGE = 1
Cmpss5RegsFile : > CMPSS5, PAGE = 1
Cmpss6RegsFile : > CMPSS6, PAGE = 1
Cmpss7RegsFile : > CMPSS7, PAGE = 1
Cmpss8RegsFile : > CMPSS8, PAGE = 1
CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
DacaRegsFile : > DACA PAGE = 1
DacbRegsFile : > DACB PAGE = 1
DaccRegsFile : > DACC PAGE = 1
DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1
DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1
DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1
/*** Warning: Only remove "Type = NOLOAD" to program OTP Locations ***/
DcsmZ1OtpFile : > DCSM_Z1_OTP, PAGE = 1, type = NOLOAD
DcsmZ2OtpFile : > DCSM_Z2_OTP, PAGE = 1, type = NOLOAD
DmaRegsFile : > DMA PAGE = 1
DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1
ECap1RegsFile : > ECAP1, PAGE = 1
ECap2RegsFile : > ECAP2, PAGE = 1
ECap3RegsFile : > ECAP3, PAGE = 1
ECap4RegsFile : > ECAP4, PAGE = 1
ECap5RegsFile : > ECAP5, PAGE = 1
ECap6RegsFile : > ECAP6, PAGE = 1
Emif1RegsFile : > EMIF1 PAGE = 1
Emif2RegsFile : > EMIF2 PAGE = 1
EPwm1RegsFile : > EPWM1, PAGE = 1
EPwm2RegsFile : > EPWM2, PAGE = 1
EPwm3RegsFile : > EPWM3, PAGE = 1
EPwm4RegsFile : > EPWM4, PAGE = 1
EPwm5RegsFile : > EPWM5, PAGE = 1
EPwm6RegsFile : > EPWM6, PAGE = 1
EPwm7RegsFile : > EPWM7, PAGE = 1
EPwm8RegsFile : > EPWM8, PAGE = 1
EPwm9RegsFile : > EPWM9, PAGE = 1
EPwm10RegsFile : > EPWM10, PAGE = 1
EPwm11RegsFile : > EPWM11, PAGE = 1
EPwm12RegsFile : > EPWM12, PAGE = 1
EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1
EQep1RegsFile : > EQEP1, PAGE = 1
EQep2RegsFile : > EQEP2, PAGE = 1
EQep3RegsFile : > EQEP3, PAGE = 1
Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1
Flash0EccRegsFile : > FLASH0_ECC PAGE = 1
Flash1CtrlRegsFile : > FLASH1_CTRL PAGE = 1
Flash1EccRegsFile : > FLASH1_ECC PAGE = 1
GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1
GpioDataRegsFile : > GPIODAT, PAGE = 1
OutputXbarRegsFile : > OUTPUT_XBAR PAGE = 1
I2caRegsFile : > I2CA, PAGE = 1
I2cbRegsFile : > I2CB, PAGE = 1
InputXbarRegsFile : > INPUT_XBAR PAGE = 1
XbarRegsFile : > XBAR PAGE = 1
FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1
RomPrefetchRegsFile : > ROMPREFETCH, PAGE = 1
MemCfgRegsFile : > MEMCFG, PAGE = 1
Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1
Emif2ConfigRegsFile : > EMIF2CONFIG, PAGE = 1
AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1
MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1
RomWaitStateRegsFile : > ROMWAITSTATE, PAGE = 1
McbspaRegsFile : > MCBSPA, PAGE = 1
McbspbRegsFile : > MCBSPB, PAGE = 1
UppRegsFile : > UPP, PAGE = 1
NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1
PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
SciaRegsFile : > SCIA, PAGE = 1
ScibRegsFile : > SCIB, PAGE = 1
ScicRegsFile : > SCIC, PAGE = 1
ScidRegsFile : > SCID, PAGE = 1
Sdfm1RegsFile : > SDFM1, PAGE = 1
Sdfm2RegsFile : > SDFM2, PAGE = 1
SpiaRegsFile : > SPIA, PAGE = 1
SpibRegsFile : > SPIB, PAGE = 1
SpicRegsFile : > ***, PAGE = 1
SpidRegsFile : > SPID, PAGE = 1
DevCfgRegsFile : > DEV_CFG, PAGE = 1
ClkCfgRegsFile : > CLK_CFG, PAGE = 1
CpuSysRegsFile : > CPU_SYS, PAGE = 1
SyncSocRegsFile : > SYNC_SOC, PAGE = 1
WdRegsFile : > WD, PAGE = 1
XintRegsFile : > XINT PAGE = 1
MemCfgRegs : > MEMCFG PAGE = 1}/*
//===========================================================================
// End of file.
//===========================================================================*/

0 programmable solution over 8 years ago in reply to Sreedhar Kaduru

Expert 1500 points

I wouldn't know what to look for from what you posted. Looks more like a map file.

Sal Pezzino told another poster he should be using

C:\ti\c2000\C2000Ware_1_00_01_00\device_support\f2837xd\common\cmd

For example 2837xD_RAM_CLA_lnk_cpu1.cmd

-------------------------------------------------------------------------------

You may go though the following thread for debugging CLA. There is a video clip on debugging the CLA.

you may wish to add the

__mdebugstop(); // add to your __interrupt void Cla1Task1 ( void ) // before you begin

https://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/541715

C2000™︎ microcontrollers

C2000 microcontrollers forum

Compiler/TMS320F28377S: CLA is not working in TMS320F28377S