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TMS320F28375D: How to organize fast and independant data access from CPU1.CLA and CPU2.CLA to an FPGA?

JoergK
Prodigy 20 points
Part Number: TMS320F28375D
Other Parts Discussed in Thread: TMS320F28377D

In my application, I need low latency fast access to external peripheral. The external component is an FPGA, hence we have the flexibility to choose any available peripheral on the TMS320F28377D. The challenge is that both CLAs need that access independent (different binary code). It seems that CPU2.CLA can not access EMIF, nor uPP.

Hence is the best recommendation that TI can make to use:
 - CPU1.CLA EMIF or uPP

-CPU2.CLA  SPI or McBSP

..or is there a more elegant way to provide low latency fast access?

  • 0
    TI__Guru** 115251 points
    Hi,

    Your understanding is correct. I would suggest using SPI because it support high speed mode which can go up 50MHz. In fact using SPI for both CLA may be even better because you can use almost same code on both side unless you need much higher throughput for CPU1.CLA hence need to use EMIF. I would not not to use uPP unless there is no other option. uPP on this device is for specific use and this IP may not be available on future C2000 devices.

    Regards.

    Vivek Singh
  • 0 in reply to Vivek Singh
    Prodigy 20 points

    Hi Vivek,

    thank you for your quick reply and helpful answer. As I understand your reply it should be possible to either use one SPI to connect both CLAs to the FPGA or use one SPI for each CLA to the FPGA to increase the thourghput.

    We have calculated that maybe the SPI interface delivers the data not fast enough. So an alternative solution for us would be to use the EMIF1 interface by CPU1.DMA and CPU2.DMA to transfer the data to the GSRAM. Then an interrupt routine on each CPU would transfer the date to the LSRAM where the CLAs would have access. Do you think this would work also to access EMIF1 by both CPUs? Would there be some bottle neck at the data transfers?