TMS320F28375D: CPU2 CLA issue

void CLA_configClaMemory(void)
{
    extern uint32_t Cla1funcsRunStart, Cla1funcsLoadStart, Cla1funcsLoadSize;

    EALLOW;

#ifdef _FLASH
    /*Copy over code from FLASH to RAM*/
    memcpy((uint32_t *) & Cla1funcsRunStart, (uint32_t *) & Cla1funcsLoadStart, (uint32_t) & Cla1funcsLoadSize);

#endif                                 /*_FLASH*/

    /*Initialize and wait for CLA1ToCPUMsgRAM*/
    MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;

    while (MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1)
    {

    };

    /*Initialize and wait for CPUToCLA1MsgRAM*/
    MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;

    while (MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1)
    {
    };

    /* Select LSxRAM to be the programming space for the CLA First configure the CLA
     * to be the master for LSx and then set the space to be a program block*/

    MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;              /*RAMLS4*/

    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;
    MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;              /*RAMLS5*/

    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;

    /* Next configure LSxRAM as data spaces for the CLA First configure the CLA
     * to be the master for LSx and the set the spaces to be Data blocks*/

    MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1;              /*RAMLS0*/

    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0;

    MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1;              /*RAMLS1*/

    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0;

    MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 1;              /*RAMLS2*/

    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 0;

    MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 1;              /*RAMLS3*/

    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 0;

    EDIS;
}

//CLA initialtization

void CLA_initCpu2Cla1(void)
{
    /* Compute all CLA task vectors On Type-1 CLAs the MVECT registers accept
     * full 16-bit task addresses as opposed to offsets used on older Type-0 CLAs*/
    EALLOW;

    Cla1Regs.MVECT1 = (uint16_t)(&Cla1Task1);
    Cla1Regs.MVECT2 = (uint16_t)(&Cla1Task2);
    Cla1Regs.MVECT3 = (uint16_t)(&Cla1Task3);
    Cla1Regs.MVECT4 = (uint16_t)(&Cla1Task4);
    Cla1Regs.MVECT5 = (uint16_t)(&Cla1Task5);
    Cla1Regs.MVECT6 = (uint16_t)(&Cla1Task6);
    Cla1Regs.MVECT7 = (uint16_t)(&Cla1Task7);
    Cla1Regs.MVECT8 = (uint16_t)(&Cla1Task8);

    /* Enable the IACK instruction to start a task on CLA in software
     * for all  8 CLA tasks. Also, globally enable all 8 tasks (or a subset of tasks)
     * by writing to their respective bits in the MIER register*/

    asm("   RPT #3 || NOP");
    Cla1Regs.MCTL.bit.IACKE = 1;
    Cla1Regs.MIER.all = 0x00FF;

    /* Configure the vectors for the end-of-task interrupt for all 8 tasks*/

    /* PieVectTable.CLA1_1_INT = &CLA1_1_ISR;
       PieVectTable.CLA1_2_INT = &CLA1_2_ISR;
       PieVectTable.CLA1_3_INT = &CLA1_3_ISR;
       PieVectTable.CLA1_4_INT = &CLA1_4_ISR;
       PieVectTable.CLA1_5_INT = &CLA1_5_ISR;
       PieVectTable.CLA1_6_INT = &CLA1_6_ISR;
       PieVectTable.CLA1_7_INT = &CLA1_7_ISR;
       PieVectTable.CLA1_8_INT = &CLA1_8_ISR; */

    /* Enable CLA interrupts at the group and subgroup levels*/
    PieCtrlRegs.PIEIER11.all = 0xFFFF;
    IER |= (M_INT11);
    EDIS;
}