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TMS320F28075: Which Interrupt for ePWM?

sagar dhavali
Intellectual 555 points
Part Number: TMS320F28075


Hello,

I have a question about interrupt generation. I am configuring my ePWM's Digital Compare submodule. Here trip 11 is configured to DCAEVT1 to cause a trip on ePWM6.
My question is, which interrupt does this DCAEVT1 generates?

I looked at the TZENT register and it says using One shot (OST) causes EPWMx_TZINT PIE Interrupt. So, similarly what interrupt occurs on trip event DCAEVT1.

I have written my configurations along with little info about TZENT from user manual.

/*************** From TZENT register: *******************/

Bit3 DCAEVT1 R/W 0h
Digital Compare Output A Event 1 Interrupt Enable
0: Disabled
1: Enabled
Reset type: SYSRSn

Bit2 OST R/W 0h
Trip-zone One-Shot Interrupt Enable
0: Disable one-shot interrupt generation
1: Enable Interrupt generation
a one-shot trip event will cause a EPWMx_TZINT PIE interrupt.
Reset type: SYSRSn

/*************** MY configurations *******************/

    //Configure EPWM output A & B to go low on trip.
    EPwm6Regs.TZCTL.bit.TZA			   = TZ_FORCE_LO;	
    EPwm6Regs.TZCTL.bit.TZB			   = TZ_FORCE_LO;
    
    //Configure DCA to be TRIP11
    EPwm6Regs.TZDCSEL.bit.DCAEVT1          	   = TZ_DCBH_HI;
    EPwm6Regs.DCTRIPSEL.bit.DCAHCOMPSEL    	   = 0xA; 			// Trip11
    EPwm6Regs.DCAHTRIPSEL.bit.TRIPINPUT11  	   = 0;				// Single trip input; Not ORed

    //Configure DCA as DCAEVT1
    EPwm6Regs.TZSEL.bit.DCAEVT1  	           = 1;				// Enable

    //Configure DCA path to be unfiltered & async
    EPwm6Regs.DCACTL.bit.EVT1SRCSEL                = DC_EVT1;
    EPwm6Regs.DCACTL.bit.EVT1FRCSYNCSEL            = DC_EVT_ASYNC;

    // Clear trip flags
    EPwm6Regs.TZCLR.bit.DCAEVT1            	   = 1;				// Writing 1 clears trip flags.
    EPwm6Regs.TZCLR.bit.INT               	   = 1;
    
    //Enable DCB interrupt
    EPwm6Regs.TZEINT.bit.DCAEVT1               = 1;

I appreciate your help.

Thanks
Sagar

  • 0
    Intellectual 555 points
    Please correct me if I am wrong.

    Since one-shot source is selected as DCAEVT1,
    EPwm6Regs.TZEINT.bit.DCAEVT1 = 1; -- This will cause EPWM6 interrupt AND
    EPwm6Regs.TZEINT.bit.OST = 1; -- This will cause EPWM6_TZ interrupt

    Am I right?
  • 0 in reply to sagar dhavali
    TI__Expert 5940 points
    Hi Sagar,

    Either a one-shot trip event or DCAEVT1 interrupt signal can generate the EPWM6_TZ interrupt with the code in your comment as you have set the OST and DCAEVT1 bits.
    You can refer to Figure 14-42. Trip-Zone Submodule Interrupt Logic in the Technical Reference Manual if you haven't already.
    This will show the possibilities of how the trip-zone interrupt can be generated.

    I also suggest reading this note in Section 14.9.2:
    "If the one-shot interrupt is enabled via the TZEINT register, and DCAEVT1 or DCBEVT1 are selected
    as OSHT trip sources via the TZSEL register, it is not necessary to also enable the DCAEVT1 or
    DCBEVT1 interrupts in the TZEINT register, as the DC events trigger interrupts through the OSHT
    mechanism."

    Regards,
    Elizabeth
  • 0 in reply to Elizabeth Joy
    Intellectual 555 points
    Thanks for the reply.
    So, upon reading the figure and the note, I understand that the difference (OST and DCAEVT1) in my comment does not matter as both causes same trip zone interrupt. (I should take care of clearing the same interrupt, of course)
    Am I right?
  • 0 in reply to Elizabeth Joy
    Intellectual 555 points

    I see that the EPWM6 outputs A & B are going low when the trip11 goes high. But I don't see the control coming to respective EPWM_TZ interrupt.

    I have enabled proper TZ interrupt in PIE vector table and have a callback as follows:

    PieCtrlRegs.PIEIER2.bit.INTx6 = 1; /* EPWM6_TZ */  /* This is init block */

PieVectTable.EPWM6_TZ_INT = &epwm_INV_2D_tzint_isr; /* This is ISR callback block */

    Anything am I doing wrong?

  • 0 in reply to sagar dhavali
    TI__Genius 15260 points

    Hi Sagar,

    Could you check the status of the various interrupt registers along the path from the EPWM to the CPU? In the EPWM, please look at TZFLG. Then also please check PIEIFR and IFR.

    You will also need a command such as "IER |= M_INT2;" to enable row 2 in the PIE.


    Regards,
    Kris

  • 0 in reply to Kris Parrent
    Intellectual 555 points
    Hi Kris,

    Respective field bits are follows:
    TZFLG -> 1
    PIEIFR -> 1
    IFR -> 0

    Yes, I have the command "IER |= M_INT2;" in my code.

    Could you please suggest something on this?

    Thank You,
    Sagar
  • 0 in reply to sagar dhavali
    TI__Genius 15260 points

    Sagar,

    Thank you for the information. This confirms that the EPWM is setup correctly to generate the interrupt. Can you step through the PIE configuration code and verify that the registers are in fact being updated? I'm wondering if there is an EALLOW or similar missing.

    Regards,

    Kris

  • 0 in reply to Kris Parrent
    Intellectual 555 points
    The following post helped me.

    e2e.ti.com/.../280892

    Thanks for your help. I really appreciate your time.

    Best Regards,
    Sagar