CCS/TMS320F28069: Code Composer Question, Command Linker file (*.cmd)

Tool/software: Code Composer Studio

TI Code Composer Linker question:

I am using TI Code Composer for TMS320F28069 DSP processor. In the linker file (.cmd), I have 7 short subroutines (0x80 bytes each) that I am moving from flash memory to RAM memory starting at RAM location 0x9000. The first 4 subroutines are staggering OK in continuous space starting from location 0x9000 but the last 3 subroutines are each starting at location 0x9000, overlapping each other.

Can anybody give me an idea what I am doing wrong in my setup? My setup is as follows:

In link.cmd (last 3 subroutines)

PAGE 0:

   L4SARAM             : origin = 0x009000, length = 0x001000

   FLASH_ABCDEFGH (R) : origin = 0x3D8000, length = 0x01CF80

   sciaRxFifoIsr     :   LOAD = FLASH_ABCDEFGH, PAGE = 0              

                         RUN = L4SARAM,         PAGE = 0

                         LOAD_START(_sciaRxFifoIsr_loadstart),

                         LOAD_SIZE(_sciaRxFifoIsr_loadsize),

                         RUN_START(_sciaRxFifoIsr_runstart)

   scibRxFifoIsr     :   LOAD = FLASH_ABCDEFGH, PAGE = 0              

                         RUN = L4SARAM,         PAGE = 0

                         LOAD_START(_scibRxFifoIsr_loadstart),

                         LOAD_SIZE(_scibRxFifoIsr_loadsize),

                          RUN_START(_scibRxFifoIsr_runstart)

   SetIdle     :   LOAD = FLASH_ABCDEFGH, PAGE = 0              

                         RUN = L4SARAM,         PAGE = 0

                         LOAD_START(_SetIdle_loadstart),

                          LOAD_SIZE(_SetIdle_loadsize),

                         RUN_START(_SetIdle_runstart)

In Flash program:

#pragma CODE_SECTION(SetIdle, "SetIdleFuncs")

void SetIdle(void)

{

                        GpioDataRegs.GPATOGGLE.bit.GPIO18 = 1;   // Test

...

}

memcpy(&SetIdle_runstart, &SetIdle_loadstart,   (Uint32)&SetIdle_loadsize);                               

Thanks for any help