TMS320F28377D: EPWM problem

Hello,
I am writing to let you know that a C2000 team member has been assigned to this post and should be answering shortly.

Regards
Baskaran

Hi fD,

How are you changing the compare values? I guess the problem is occuring because the compare values are not getting periodically updated in shadow register between the ctr = 0 and ctr = prd events. The compare values will be loaded from the shadow to active registers in these events. You can try disabling the shadow mode.

Thanks
Vasudha

Thank you for your help.

Sorry,I didn't describe the problem exactly.In my project ,the HRPWM is used and I want to synchronize the EPWM1 and EPWM2. EPWM1 is the master module,and at  EPWM1 CTR=ZERO,the sync plus is generated.The configurations are as follow:

 

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; /
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; 
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; 
EPwm1Regs.TBCTL.bit.SYNCOSEL =TB_CTR_ZERO; 
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; 
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.FREE_SOFT = 0x0;
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; 
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; 
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;/
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;

// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; 
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; 
EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; 

EPwm1Regs.AQSFRC.bit.RLDCSF = 3; 
EPwm1Regs.AQCSFRC.bit.CSFA = AQC_NO_ACTION; 
EPwm1Regs.AQCSFRC.bit.CSFB = AQC_NO_ACTION;

....

EPwm1Regs.HRCNFG.all = 0x0;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; 
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; 
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; 
EPwm1Regs.HRCNFG.bit.EDGMODEB = HR_BEP;
EPwm1Regs.HRCNFG.bit.CTLMODEB = HR_CMP;
EPwm1Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO_PRD;
EPwm1Regs.HRCNFG.bit.AUTOCONV = 1; 
EPwm1Regs.HRPCTL.bit.HRPE = 1; 
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = TB_DISABLE;
EPwm1Regs.HRCNFG2.bit.CTLMODEDBFED = 2;
EPwm1Regs.HRCNFG2.bit.CTLMODEDBRED = 2;
EPwm1Regs.HRCNFG2.bit.EDGMODEDB = 3;

I find that if I change the bold configuration above,like this ,EPwm1Regs.HRPCTL.bit.HRPE = 0;,it can work normally.  

In theTechnical Reference Manual,it says,

NOTE: When high-resolution period mode is enabled, an EPWMxSYNC pulse will introduce +/- 1 - 2
cycle jitter to the PWM (+/- 1 cycle in up-count mode and +/- 2 cycle in up-down count
mode). For this reason, TBCTL[SYNCOSEL] should not be set to 1 (CTR = 0 is
EPWMxSYNCO source) or 2 (CTR = CMPB is EPWMxSYNCO source). Otherwise, the jitter
will occur on every PWM cycle with the synchronization pulse.
When TBCTL[SYNCOSEL] = 0 (EPWMxSYNCI is EPWMxSYNCO source), a software
synchronization pulse should be issued only once during high-resolution period initialization.
If a software sync pulse is applied while the PWM is running, the jitter will appear on the
PWM output at the time of the sync pulse.

So I think my problem is related to the HRPWM configurations .what is the problem?

Can you give me an example about how to use the HRPWM and  synchronize the EPWM modules?

Thank you.

What about ePWM synchronization using CpuSysRegs.PCLKCR0.bit.TBCLKSYNC ? You need to write 0 to it, init all ePWMs with different initial TBCTR if you need different phases, then set TBCLKSYNC=1.

Thanks for your advice.

I think using CpuSysRegs.PCLKCR0.bit.TBCLKSYNCI is not enough.In my project  the phase and frequency should be changed periodically for frequencymodulation and phase shift control .So,the 'master and slave mode 'need to be used. However,I have encountered some problems about HREPWM mode with high resolution period control as described above.The experiments show that the problem is related to EPWM's  high resolution period control mode .I have referenced all the documents which I can look for,but can't find a  solution.So are there some Application guidances about HRPWM for high resolution period control? 

Thanks .