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TMS320F28069: Timers Interrupt on TI TMS320F28069

Zeke Shashoua
Prodigy 80 points
Part Number: TMS320F28069


Timers Interrupts on TI TMS320F28069:

 

I am using three timers interrupt routines (Timer 0,1,2). Timer1 and Timer2 is my concern.

Timer1 runs once a second for 2 milliseconds (execute a long routine).

Timer 2 runs every 60 micro seconds for 20 micro seconds (execute a short routine).

 

The question; Is there a way for Timer2 to interrupt Timer1 so that Timer2 can always run every 60 micro seconds without missing any interrupts?

 

Currently, when Timer1 is running, Timer2 has to wait till timer1 finishes its 2 milliseconds code execution.

Thanks for any help

  • 0
    TI__Intellectual 835 points

    Hello,

    Your problem is of having a nested interrupt. By default, C2000 does not support a nested interrupt. However, you can do that using software.

    A similar problem is discussed in this thread: https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/21121

    The following Answer by Frank Borman will help you understand the sequence of your code:

    "the default operating mode of the C28x regarding interrupts is "No - Nested". However, you can overrule this into a "Nested" system by your own code.

    The default no-nested sequence is this:

    ISR1:

    1. Hardware context save, including INTM and IER

    2. Hardware disables INTM and the corresponding IER-bit

    3. Your ISR1 code is executed, including ACK of the PIE

    4. Hardware context restore, including the status of INTM and IER as they were set upon entry.

    A nested  interrupt - system would look like this:

    ISR1:

    1. Hardware context save, including INTM and IER

    2. Hardware disables INTM and the corresponding IER-bit

    3. You enable those IER-lines, which you would like to be able to interrupt ISR1, while ISR1 is still running. Also, enable INTM now. Do also a PIE-ACK here, if your higher prioritized INT is within the same PIE group.

    4. Execute your ISR1 code here.  If your higher prioritized ISR (which you enabled in step3) is triggered and it's ISR will interrupt the running ISR1 code.

    5. Hardware context restore, including the original status of INTM and IER upon entry at step1.

    ISR2:

    Same sequence as for ISR1. In step 3 you can qualify other interrupt sources to be of higher priority  than ISR2."

    Please try this out. In case you need any further assistance, do tell.

  • 0 in reply to Ritvik Sadana1
    Prodigy 80 points
    Great thanks, this resolved my interrupts problem