Part Number: TMS320F28335
Other Parts Discussed in Thread: C2000WARE
As part of a development for Airbus Helicopters, I have to cover a req related to an errata of the DSP.
The F28335 DSP transmits and receives CAN frames by using ECAN-A
F28335 DSP transmits each 50 ms 12 frames (in sequence) from 12 different mailboxes.
Errata is:
Advisory eCAN: Unexpected Cessation of Transmit Operation
Revision(s) Affected 0, A
Details In rare instances, the cessation of message transmission from the eCAN module has
been observed (while the receive operation continues normally). This anomalous state
may occur without any error frames on the bus.
Workaround(s) The Time-out feature (MOTO) of the eCAN module may be employed to detect this
condition. When this occurs, set and clear the CCR bit (using the CCE bit for verification)
to remove the anomalous condition.
To cover, I code the following:
- MOTO registers are initialized with values as 500 µs for first message, 1000 µs for next … and so on. (with CAN speed set to 500 Kb/s and DLC set to 8 bytes, max transmission value is around 280 µs)
- CANTSC is cleared each 50 ms before sending the CAN frames
- CANTOC is set with a bit set for each message sent.
With a serial debugger, I see that MOTS registers are valid values (for all the messages sent):
- 0x9C for first value 312 µs (2 µs resolution as 500 Kb/s)
- 0x12C for second 600 µs Delta = 288 µs
- 0x1B8 880 µs Delta = 280 µs
- 0x246 1164 µs Delta = 284 µs
- 0x2D1, 0x35D, 0x3E9 …
I want next, verify that if the message is not sent before MOTO value, CANTOS bit is set.
So I change with debugger MOTO value: by example, I change first MOTO value with 0x01 (instead of 0xFA = 500 µs (2 µs resolution)
I can see that CANTOS bit 0 toggles 0 /1, (as time out is always set, why CANTOS bit is not always set ? )
Same for any other MOTO value changed.
As the workaround specifies the use of MOTO:
- The Time-out feature (MOTO) of the eCAN module may be employed to detect this condition.
With the simple example described before, CANTOS bit is not systematically set :
how can I do to be sure that
Unexpected Cessation of Transmit Operation
Will be always detected?
May i clear MOTS values before sending and verify after transmission that all MOTS values are lower than MOTO values (software function ?)
Can you send me examples of code to workaround the errata?
Can you detail more?
When this occurs, set and clear the CCR bit (using the CCE bit for verification) to remove the anomalous condition
I saw there is a state machine running : how does it work ? What is the state machine frequency ?
Any additional information will be appreciated
Salutations
