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LAUNCHXL-F28377S: LAUNCHXL-F28377S

Part Number: LAUNCHXL-F28377S

Acqusition Time Problem

Hello,

My problem is as follows:

I am trying to measure ADC time. For this, I am using the least required "ACQPS".  For example;

My single adc reads in 80nanosec. For this, least required ACQPS is 15. In doing so, I am able to read adc without any problem. However, as I increase ACQPS value, I see change in my ADC reading time. It is the part that I have not understood. In datasheet attached below, in section 9.1.4.3 it is written that  "The selected acquisition window duration must be at least as long as one ADCCLK cycle." I do not see any reason in the change of ADC reading time as I increase ACQPS value since datasheet has not stated the maximum value to which ACQPS can be increased.

The time for ADC is measured likewise that of the code given below.  

AdcaRegs.ADCSOCFRC1.all = 0x0001;

GpioDataRegs.GPASET.bit.GPIO13=1;  //start adc time

while(0 == AdcaRegs.ADCINTFLG.bit.ADCINT1);

AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;

AdcaResults = AdcaResultRegs.ADCRESULT0;

GpioDataRegs.GPACLEAR.bit.GPIO13=1;   //finish adc time

AdcaRegs.ADCINTSEL1N2.bit.INT1E = 0;

spruhx5c.pdf

  • Hi,

    Looks like your measuring time routine uses an external GPIO to mark the start of conversion and end of conversion and inspecting the pulse width on a scope to determine the start and stop of conversion, or what you refer to as ADC time.

    With the GPIO methodology, adjusting ACQPS would affect the start /stop position of the marker.  Please refer to the ADC Timing Diagram (Section 9.2.1, p. 1200).  The moment you issue a set high command on the external pin, the SOC (start of conversion) signal is already set to high from the previous statement (AdcaRegs.ADCSOCFRC1.all = 0x1).  Once this SOC is set, the controller ensures that the signal in ADC channel specified  will be captured or sampled with the duration programmed in the ACQPS register.  Referring to the AC Timing diagram, the GPIO start pulse would coincide with the start of ADC S+H (3rd row in the timing diagram) and its duration will vary depending on how many SYSCLK cycles you specified in the ACQPS register.   ACQPS is variable as some external circuits may need more time to be sampled accurately.  Generally, for higher impedance input circuit, you would need more sampling time (higher ACQPS) to allow enough time for a signal to settle to an acceptable level before it is converted.  Lower impedance input circuit  require the minimum ACQPS as signal would have settled pretty quickly.  Once sampling is done (upon waiting for the ACQPS cycles to have transpired), the ADC would quantify the signal to a digital level.  This will also take some time and this will be dependent on how fast the ADC clock is running.  There is a table also in the timing diagram section that shows the number of clock cycles needed to convert the digital signal.  In both the timing  and clock diagrams, this is denoted by the tLAT parameter.  This is also the time when the ADC interrupt signal becomes active (in your above example, ADCINT1 going high means that the ADC has completed converting and results are available).  Again, back to your ADC routines above, after polling for ADCINT1 and reading the results, the GPIO is cleared.  What you are observing in with the GPIO duration just confirms that sampling time (ACQPS) is a function of how fast the ADC converts (also referred to as ADC throughput).

    Hope this explains what you are observing.

    Regards,

    Joseph

  • Joseph, problem have been solved in your answer's guide. Thank you.