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TMS320F28035: PWM Interrupt Latency: Min and Max

andrew barnett66202
Intellectual 270 points
Part Number: TMS320F28035

Documentation I have states that the minimum interrupt latency is 14 cycles from an internal interrupt.  In my application this would be a PWM CMPA match.  

How consistent is the 14 cycle latency?  Can it ever be less?  If it can be more cycles, what is the maximum number of cycles?

Is there documentation that describes the latency in detail?

Thanks in advance 

  • 0
    TI__Mastermind 27200 points

    Andrew,

    The 14 cycle latency refers to the hardware auto-context save which takes place when the CPU core takes an interrupt.  Interrupt latency can never be less than this.

    This represents a minimal context. If your ISR is written in C, the compiler will execute additional register pushes to the stack to protect whatever it uses in the ISR.  The number will depend on what is being used.  An interrupt may be further delayed for a couple of reasons, including uninterruptible code being executed (e.g. long FIR filter), or if the user has INTM set.  Memory wait states will also play a role if, for example, the ISR is slower speed memory.

    In the absence of these, the maximum number of cycles would be incurred when all registers are saved to stack. For a fixed point C28x you would have an additional eight 32-but register pushes to perform:

    PUSH AR1H:AR0H ; Save other registers if used
    PUSH XAR2
    PUSH XAR3
    PUSH XAR4
    PUSH XAR5
    PUSH XAR6
    PUSH XAR7
    PUSH XT

    A floating point core would need to save an additional ten registers on top of these, so I think the maximum would be 32.  If coding the ISR in assembly you obviously control this.

    Further information can be found in chapter 3 of the CPU user's guide for the C28x core:

    www.ti.com/.../spru430f.pdf

    ...and in the FPU reference guide:

    www.ti.com/.../sprueo2b.pdf

    Also, you may find this Wiki page helpful:

    processors.wiki.ti.com/.../Interrupt_Nesting_on_C28x

    Regards,

    Richard

    8311.C28x Interrupt Latency.pdf

  • 0 in reply to Richard Poley
    Intellectual 270 points
    Thank you Richard.

    Will the latency be more consistant if I run out of RAM?
  • 0 in reply to andrew barnett66202
    TI__Mastermind 27200 points
    You are welcome. It should be just as consistent, but you will measure slightly lower latency because the first instruction in the ISR will be fetched from zero wait state memory. Of course, the ISR will execute faster from RAM too.

    Regards,

    Richard