CCS/TMS320F28377D: SDFM data reset after sync signal from ePWM

Willie,

Sorry, your question isn't clear and I believe there are lot of important information missing:-

1) DOSR settings?

2) EPWM settings:-
- TBPRD settings
- CMPC / CMPD settings
- PWM frequency

I get a feeling that you don't prefer to use SDFM data acknowledge interrupts to read SDFM data filter results and you want to use PWM1/2 interrupt to read the SDFM data filter. Am I correct? If so, after EPWM11/12 SDSYNC signal resets the SDFM data filter you have to time PWM1/2 interrupt to wait for latency of data filter + 5 SD-Cx cycles.

Regards,
Manoj

Manoj,

Sorry for the unclear information, here they are:
1) SDFM settings:
-DOSR:256
-Filter: sinc3
-CLK: 10MHz
-MIF: disable
-Reset: enable

2) EPWM settings:-
- TBPRD : 6250 (up-down count)
- CMPC / CMPD : 4140
- PWM frequency: 8K

3) CLA trigger source settings:-
- trigger source: ePWM2 CMPC up-count
- CMPC: 3940

And yes, I don't use SDFM AEFx to trigger latch function, I use another ePWM counter to trigger CLA at the right time.
The time was 3 * (256 / 10M) + 10 SDFM CLK.

3 * (256 / 10M) + 10 SDFM CLK. = 3940

My question is:
Will the SDFM data register also be reset when sync signal happened?
According to spec, the register data wont be clear after sync signal, however, if I set ePWM11.CMPC = ePWM2.CMPC = 3940 , then I will get 0.

Willie

Willie,

Yes, as the TRM mentions data filter register doesn't get reset to 0.

Based on your SDFM, SD-modulator frequency settings, you have to wait for ((3*256) + 5) / 10MHz = 77.3 us after data filter gets SDSYNC pulse from PWM. I didn't quite understand your diagram. Also, with PWMCLK freq = 8KHz, TBCTR increments / decrements every 125 us. Why is PWMCLK freq so slow?

Regards,
Manoj

Manoj,
Thanks for your reply.
There is a mistake on describing the PWMCLK freq, I just means that our PWM is trigger at zero, and the period in real world is 125us, not means PWMCLK freq = 8KHz.

As you mention,
"Yes, as the TRM mentions data filter register doesn't get reset to 0."
But, I found that register data is been cleared when sync, just like question 2 on this post:
e2e.ti.com/.../624783

Manoj,

I still get 0 after latch data after sync signal add latency of data filter + 5 SD-Cx.
Does it allowable to reset the modelu directly at latch? which means reset again after add latency of data filter + 5 SD-Cx.

Willie,

I couldn't understand your question. Please rephrase it.

What is the expected digital output? Did you make sure to read the SDFM data filter results after ((3*256) + 5) / 10MHz = 77.3 us after SDSYNC event?

Regards,
Manoj

Manoj, 

For safety reason, I read data after  ((3*256) + 10) / 10MHz = 78.3 us after SDSYNC event.

But the next SDSYNC event by ePWM11 also trigger after 78.3 us after last SDSYNC event.

Read and SDSYNC are at the same time.

According to my experiment, to avoid reading 0, the next SDSYNC must delay 2us, otherwise I got 0.

I read data at CLA which is triggered by PWM counter, Is it possible that CLA is too slow so SDFM data register is cleaned for the first data after SDSYNC?

Manoj, 

Manoj Santha Mohan said:

I also don't see why you need of additional 5 SD-Cx. Reading the result at ((3*256) + 5) / 10MHz = 77.3 us should get you correct filter output result.

Adding 5 SD_Cx is experiment result, maybe I did something wrong, I'll check these days.

Manoj Santha Mohan said:

Also, you cannot read the filter output / reset the data filter at the same time. This can lead to unpredictable results. That probably why you are seeing 0 in your result register.

So, how long dose TI suggest the time interval between read and reset?

If user cannot read and reset at the same time, the TRM notes "reset won't clear data" is non-sense. Or, is there an application that use this feature?

Willie,

I'm not sure about your application requirement. But, I can say we have never had customers who want to reset and read the SDFM data filter at the same time.

Regards,
Manoj