F28M36P63C2: Handling I2C NACK correctly

The nice wiki on I2C http://processors.wiki.ti.com/index.php/I2C_Tips has two ways to handle a NACK while transmitting.

First in the 'Repeat Start' section, it suggests setting the CMD register to 0 to release the SCL.

if ( *I2C_ICSTR & ICSTR_NACK )
{
    *I2C_ICMDR = 0;        // reset I2C so SCL isn't held low
    return RRET__FAIL;
}

But in the 'Detecting and handling NACK' it has the following, where it issues a STOP command and then clears the NACK from the status register:

// If a NACK occurred, SCL is held low and STP bit cleared
if ( *I2C_STR & ICSTR_NACK )
{
    *I2C_MDR |= ICMDR_STP;    // send STP to end transfer
    *I2C_STR = ICSTR_NACK;    // clear NACK bit
    return I2C_FAIL;
}

What is the appropriate response? Clarifying the wiki would be appreciated.