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TMS320F28027: Fetch GPADAT in 4 cycles

Pavel Livshits93402
Prodigy 150 points
Part Number: TMS320F28027

Hello,

I working with piccolo EVM board for 28027 and I need to read the lower 16 bits of GPIO and write into int16_t array. The catch it that each cycle of reading GPADAT and writing into memory should take exactly 4 cycles as the GPADAT changes every 4 cycles and loop it for N times. I tried many approaches with MOV but the best I could do is put GPADAT onto AL (ACC) and then AL to GPADAT which takes much more like 16  cycles (according to CCS v7 clock counter) and loop with BANZ breaks the pipe so I'm far away to reach my goal.

ReadData:
    MOV AL, *+XAR3[0]
    MOV *XAR4++, AL
    BANZ ReadData,AR0--

I accept that under such dependencies I probably need to call the same lines again an again but at least I need to be sure that it takes 4 cycles. 

I'll appreciate this forum help!

Thanks,

Pavel 

  • 0
    TI__Mastermind 27200 points
    Pavel,
    Yes, you're not going to get there with a BANZ because of the pipeline flush. Keep in mind that the GPADAT register is located in peripheral frame 1, which has 2 wait-states on read accesses. I cannot account for the 16 clock cycles you're seeing in CCS - on my machine a BP on the first instruction after the label comes back in 6 cycles.
    Is 'N'fixed and known? If so, you could obviously accomplish this by simply writing out the instruction pairs. For example:
    NOP
    MOV AL, *+XAR3[0]
    MOV *XAR4++, AL
    MOV AL, *+XAR3[0]
    MOV *XAR4++, AL
    MOV AL, *+XAR3[0]
    MOV *XAR4++, AL
    MOV AL, *+XAR3[0]
    MOV *XAR4++, AL
    MOV AL, *+XAR3[0]
    MOV *XAR4++, AL
    NOP
    On my machine this runs in 21 cycles between the NOPs, which I think is correct allowing for the wait states. Is this feasible?
    Regards,
    Richard
  • 0 in reply to Richard Poley
    Prodigy 150 points
    Hi Richard,

    Thank you I will try your suggestion. The XAR4 points to array in RAM, so 2 cycles between consequent writings will be enough?

    Thanks,
    Pavel
  • 0 in reply to Pavel Livshits93402
    TI__Mastermind 27200 points
    Hi Pavel,
    Correct. RAM has zero read/write wait states so there will be no problem with that.
    The wait states are on p.52 of the datasheet:
    www.ti.com/.../tms320f28027.pdf
    Regards,
    Richard