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In my board i'm giving 50 hz 3 volt sine wave to ADCINB1 but when i plot the graph of ADCRESULT9 is in the graph. What is the problem ??? My ISR frequency 50 Khz.
/*
* ======== main.c ========
*/
#include <xdc/std.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include "DSP28x_Project.h"
#include "Solar_F.h"
#include "IQmathLib.h"
#pragma DATA_SECTION(sine_table,"IQmathTables");
_iq30 sine_table[512];
SPLL_1ph_F spll1;
SPLL_1ph_F_NOTCH_COEFF spll_notch_coef1;
#define GRID_FREQ 50.0
#define ISR_FREQUENCY 50000.0
#define PI 3.14
void initADC();
void adcTimerFxn(void);
Void adcHwiISR(void);
float32 temp=0;
/*
* ======== main ========
*/
Int main()
{
//-----------------------------------------------------
InitSysCtrl();
initADC();
IER = 0x0000;
IFR = 0x0000;
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0;
EDIS;
EPwm1Regs.TBPRD = 2250; // Period = 2´600 TBCLK counts // 45 Mhz frekanslı 600 defa sayıyor
EPwm1Regs.CMPA.half.CMPA =1125;
// EPwm1Regs.CMPB = 7200; // Compare B = 500 TBCLK counts
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Set Phase register to zero
EPwm1Regs.TBCTR = 0; // clear TB counter
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetric
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero
// EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
// EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;
// EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;
// EPwm1Regs.AQCTLB.bit.CBD = AQ_SET;
//EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
//EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
// EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;
// EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR;
/*
EPwm1Regs.TBCTL.all = 0;
EPwm1Regs.TBCTL.bit.CLKDIV = 0;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm1Regs.TBCTL.bit.CTRMODE = 2;
EPwm1Regs.AQCTLA.all = 0x0006;
EPwm1Regs.TBPRD = 7200;
EPwm1Regs.CMPA.half.CMPA = 3600;
EPwm1Regs.AQCTLA.all = 0x0060;
EPwm1Regs.ETSEL.all = 0;
EPwm1Regs.ETSEL.bit.INTEN = 1;
EPwm1Regs.ETSEL.bit.INTSEL = 5;
EPwm1Regs.ETPS.bit.INTPRD = 1;
*/
SPLL_1ph_F_init(GRID_FREQ,((float)(1.0/ISR_FREQUENCY)), &spll1);
SPLL_1ph_F_notch_coeff_update(((float)(1.0/ISR_FREQUENCY)), (float)(2*PI*GRID_FREQ*2),(float)0.00001,(float)0.1, &spll1);
//-----------------------------------------------------
BIOS_start(); /* does not return */
return(0);
}
void adcTimerFxn(void)
{
AdcRegs.ADCSOCFRC1.bit.SOC9=1;
while(AdcRegs.ADCINTFLG.bit.ADCINT1 == 0) {}
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
spll1.AC_input = ((float32)AdcResult.ADCRESULT9-1862)/(float32)1862; // SPLL call
SPLL_1ph_F_MACRO(spll1);
temp = (((spll1.sin[1])+1.0)/2)*EPwm1Regs.TBPRD;
EPwm1Regs.CMPA.half.CMPA =EPwm1Regs.TBPRD - _IQsat(temp,EPwm1Regs.TBPRD,0);
}
void initADC()
{
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
(*Device_cal)();
AdcRegs.ADCCTL1.bit.ADCBGPWD = 1; // Power ADC BG
AdcRegs.ADCCTL1.bit.ADCREFPWD = 1; // Power reference
AdcRegs.ADCCTL1.bit.ADCPWDN = 1; // Power ADC
AdcRegs.ADCCTL1.bit.ADCENABLE = 1; // Enable ADC
AdcRegs.ADCCTL1.bit.ADCREFSEL = 0; // Select interal BG
AdcRegs.ADCCTL2.bit.CLKDIV2EN = 1;
AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap mode
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; // ADCINT1 trips after AdcResults latch
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; // Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 9; // setup EOC1 to trigger ADCINT1 to fire
AdcRegs.SOCPRICTL.bit.ONESHOT = 1 ;
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0x0; // set SOC0 channel select to ADCINA0
AdcRegs.ADCSOC1CTL.bit.CHSEL = 0x1;
AdcRegs.ADCSOC2CTL.bit.CHSEL = 0x2;
AdcRegs.ADCSOC3CTL.bit.CHSEL = 0x3;
AdcRegs.ADCSOC4CTL.bit.CHSEL = 0x4;
AdcRegs.ADCSOC5CTL.bit.CHSEL = 0x5;
AdcRegs.ADCSOC6CTL.bit.CHSEL = 0x6;
AdcRegs.ADCSOC7CTL.bit.CHSEL = 0x7;
AdcRegs.ADCSOC8CTL.bit.CHSEL = 0x8;
AdcRegs.ADCSOC9CTL.bit.CHSEL = 0x9;
AdcRegs.ADCSOC10CTL.bit.CHSEL = 0xA;
AdcRegs.ADCSOC11CTL.bit.CHSEL = 0xB;
AdcRegs.ADCSOC12CTL.bit.CHSEL = 0xC;
AdcRegs.ADCSOC13CTL.bit.CHSEL = 0xD;
AdcRegs.ADCSOC14CTL.bit.CHSEL = 0xE;
AdcRegs.ADCSOC15CTL.bit.CHSEL = 0xF;
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 0; // set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 0; // set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 0; // set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 0; // set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 0; // set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC
AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 0; // set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC6CTL.bit.TRIGSEL = 0; // set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC
AdcRegs.ADCSOC7CTL.bit.TRIGSEL = 0; // set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC8CTL.bit.TRIGSEL = 0; // set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC
AdcRegs.ADCSOC9CTL.bit.TRIGSEL = 0; // set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC10CTL.bit.TRIGSEL = 0; // set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC
AdcRegs.ADCSOC11CTL.bit.TRIGSEL = 0; // set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC12CTL.bit.TRIGSEL = 0; // set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC
AdcRegs.ADCSOC13CTL.bit.TRIGSEL = 0; // set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC14CTL.bit.TRIGSEL = 0; // set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC
AdcRegs.ADCSOC15CTL.bit.TRIGSEL = 0; // set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC3CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC4CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC5CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC6CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC7CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC8CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC9CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC10CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC11CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC12CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC13CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC14CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC15CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
IER |= M_INT1; // Enable CPU Interrupt 1
EDIS;
}
/*
Void adcHwiISR()
{
spll1.AC_input = ((float32)AdcResult.ADCRESULT9-1900)/(float32)1900; // SPLL call
SPLL_1ph_F_FUNC(&spll1);
temp = (((spll1.sin[1])+1.0)/2)*EPwm1Regs.TBPRD;
EPwm1Regs.CMPA.half.CMPA =EPwm1Regs.TBPRD - _IQsat(temp,EPwm1Regs.TBPRD,0);
// AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
// Clear INT SEQ1 bit
/* static unsigned int index = 0;
EPwm1Regs.CMPA.half.CMPA = EPwm1Regs.TBPRD -_IQsat(((((float32)sine_table[index]/1073741824.0+0.9999)/2)*EPwm1Regs.TBPRD),EPwm1Regs.TBPRD,0);
if (index++ >511) index = 0;
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Clear INT SEQ1 bit
*/
/*
-------------------------------------------------------------------------
ÇALIŞAN KOD
static unsigned int index = 0;
spll1.AC_input = ((float32)(sine_table[index]/1073741824.0)); // SPLL call
SPLL_1ph_F_FUNC(&spll1);
temp = (((spll1.sin[1])+1.0)/2)*EPwm1Regs.TBPRD;
EPwm1Regs.CMPA.half.CMPA =EPwm1Regs.TBPRD - _IQsat(temp,EPwm1Regs.TBPRD,0);
if (index++ >511) index = 0;
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Clear INT SEQ1 bit
----------------------------------------------------------------------------
*/
/*
spll1.AC_input = ((float32)AdcResult.ADCRESULT9-1870)/(float32)1870; // SPLL call
SPLL_1ph_F_FUNC(&spll1);
temp = (((spll1.sin[1])+1.0)/2)*EPwm1Regs.TBPRD;
EPwm1Regs.CMPA.half.CMPA =EPwm1Regs.TBPRD - _IQsat(temp,EPwm1Regs.TBPRD,0);
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Clear INT SEQ1 bit
*/
/*
spll1.AC_input = ((float32)AdcResult.ADCRESULT9-1870)/(float32)1870; // SPLL call
SPLL_1ph_F_FUNC(&spll1);
temp = ((spll1.sin[1]+0.9999)/2)*EPwm1Regs.TBPRD;
EPwm1Regs.CMPA.half.CMPA =EPwm1Regs.TBPRD - _IQsat(temp,EPwm1Regs.TBPRD,0);
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Clear INT SEQ1 bit
*/
/*
}
*/
