CCS/TMS320F28379D: SCIA Settings for Receive Interrupt and Echoback

InitPieCtrl();

//
// Disable CPU __interrupts and clear all CPU __interrupt flags:
//
   IER = 0x0000;
   IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the __interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.

InitPieVectTable();
   EALLOW;  
      PieVectTable.SCIA_RX_INT = &sciaRxFifoIsr;

   EDIS; 
   
   scia_fifo_init();       // Initialize the SCI FIFO
   scia_echoback_init();   // Initialize SCI for echoback

   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
   PieCtrlRegs.PIEIER9.bit.INTx1 = 1;   // PIE Group 9, INT1
   PieCtrlRegs.PIEIER9.bit.INTx2 = 1;   // PIE Group 9, INT2
   IER = 0x100;                         // Enable CPU INT
   EINT;

void scia_echoback_init()
{
    SciaRegs.SCICCR.all = 0x0007;   
                                    
    SciaRegs.SCICTL1.all = 0x0003;  
    SciaRegs.SCICTL2.all = 0x0003;
    SciaRegs.SCICTL2.bit.TXINTENA = 1;
    SciaRegs.SCICTL2.bit.RXBKINTENA = 1;

    
    SciaRegs.SCIHBAUD.all = 0x0000;
    SciaRegs.SCILBAUD.all = 0x00C2;

    SciaRegs.SCICTL1.all = 0x0023;  
}

interrupt void sciaRxFifoIsr(void)
{
    Uint16 i;

    i=SciaRegs.SCIRXBUF.all;  // Read data

    scia_xmit(i);

    SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;   
    SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;   

    SciaRegs.SCIRXST.bit.RXRDY=1;

    PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;      
}

void scia_fifo_init()
{
    SciaRegs.SCIFFTX.all = 0xE040;
    SciaRegs.SCIFFRX.all = 0x2044;
    SciaRegs.SCIFFCT.all = 0x0;
}