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CCS/TMS320F28377D: Generating phase shift between two signals of same EPWM channel (i.e. EPWM1A and EPWM1B)

Md%20Mejbaul%20Haque
Intellectual 330 points
Part Number: TMS320F28377D

Tool/software: Code Composer Studio

Hi all,

I can generate required phase shift between two signals of different EPWM channel. For example, I can generate a phase shift between EPWM 1 and EPWM 2 channel. This code works fine.

Now I am wanting to introduce phase shift between signal from same EPWM channel. For example. I require a phase shift between EPWM1A and EPWM 1B. 

Con anyone please help me how can this be done?

Regards,

Haque

  • 0
    TI__Genius 15260 points

    Hi Haque,

    There is not a built in method for doing phase shift between EPWM channels of the same module as there is with separate EPWM modules.

    You would need to use different compare values and action qualifier events to achieve it within the same module. The easiest way to achieve this would be using up-down count mode. This is because you will essentially have more compare events because you can create different actions for CMPA/B when the counter is counting up and separate actions when the counter is counting down.

    Regards,

    Kris

  • 0 in reply to Kris Parrent
    Intellectual 330 points
    Hi Kris,

    Thanks for you comments. Yes I understand it is difficult to get within same EPWM modules. Therefore I have used separate six EPWM modules and can introduce a fixed phase shift between the six signals.

    Now what I need is to vary the phase shift between the modules (not fixed) and I think I need to update the phase shift register (EPwm1Regs.TBPHS.bit.TBPHS).

    Can you please advise me how can I do it? Please take below two PWM module as an example case.

    Best regards,
    Haque

    void configure_pwm1()
    {
    EPwm1Regs.TBPRD = 1250; // Set timer period
    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
    EPwm1Regs.TBCTR = 0x0000; // Clear counter

    // Setup TBCLK
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading - Master Module
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;
    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //set duty cycles for series converter
    duty_p1 = (float) PWM_PERIOD / 2;
    EPwm1Regs.CMPA.bit.CMPA = (int) duty_p1;
    EPwm1Regs.CMPB.bit.CMPB = (int) duty_p1;

    // Set actions
    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
    }

    void configure_pwm2()
    {
    EPwm2Regs.TBPRD = 1250; // Set timer period
    EPwm2Regs.TBPHS.bit.TBPHS = 156.2; // Phase is 22.5 degree (TBPHS 156)
    EPwm2Regs.TBCTR = 0x0000; // Clear counter

    // Setup TBCLK
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // // Slave module -Enable phase loading
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2;
    EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=120 deg)
    EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;


    duty_p2 = (float) PWM_PERIOD / 2;
    EPwm2Regs.CMPA.bit.CMPA = (int) duty_p2;
    EPwm2Regs.CMPB.bit.CMPB = (int) duty_p2;

    // Set actions
    EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
    EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;

    }
  • 0 in reply to Md%20Mejbaul%20Haque
    TI__Genius 15755 points

    Hi Haque,

    Sorry for the late reply.

    "Now what I need is to vary the phase shift between the modules (not fixed) and I think I need to update the phase shift register (EPwm1Regs.TBPHS.bit.TBPHS)."

    Yes, you are right. You need to update the TBPHS in your ISR. 

    I have two suggestions:

    1. Since you are using up-down count mode, you need to be careful on setting the PHSDIR register. 

    2. Also please pay attention to the comparator value during the transition, sometimes it needs to be updated together with the TBPHS in case of missing compare events. You can refer to the thread below and the phase shift full bridge application report which utilizes the variable TBPHS. There is also a HVPSFB project in the controlSUIT for your reference.

    e2e.ti.com/.../675947

    Thanks.

    Best regards,

    Chen

  • 0 in reply to Chen Jiang ti
    Intellectual 330 points
    Hello Chen,

    Thank you for your reply. I am working working on it.

    However, could you please look at the above code and add a few lines of code where should I change exactly to get it properly done?

    Best regards,
    Haque
  • 0 in reply to Md%20Mejbaul%20Haque
    TI__Genius 15755 points
    Hi Haque,

    I can not help you add the code. Your original code seems ok. However, I think you probably could take a look at the "14.4.3.2 Time-Base Clock Synchronization" in Technical Reference Manual of f2837x and follow the procedure to set up your synchronization in your initialization code and add more code in the ISR to update the TBPHS. Also please pay attention to the Figure 14-7. Time-Base Counter Synchronization Scheme when configuring the sync chain propagation path.
    Above all, I still think the HVPSFB project I mentioned before in the controlSUIT should help you a lot to get start with.
    Hope this helps.

    Best regards,
    Chen