C2000 Team,
We have a customer investigating 30 MHz clock signals and both rising and falling edges are not what as steep as expected.
Measured 10% to 90% rise time is 7.2ns so the actual rise time is about 6.2ns. (I do have a picture...) That is, the clock signal is out of DSP specification. Now, I have few questions:
Q1: I didn’t find clear specification how you specify rise time but I assume you mean 10% to 90% rise time. I.e. for 3.0V signal the time is sitting between voltage levels of 0.30V and 2.7V. Is that correct?
Q2: Is 6.2ns rise time already a problem for DSP performance or do you have some safety margins? How big margins do you have? I mean, what would be an ultimate rise time I should never exceed?
Page 48 of the data manual specifies the rise and fall times of the clock, but can you provide some feedback as it relates tot he performance margins. Your assistance would be greatly appreciated.
