This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28069: ePWM on power ON and configuration

Part Number: TMS320F28069
Other Parts Discussed in Thread: CONTROLSUITE

Please tell me how should I keep PWM to low state on power ON. Even by pulling down pins and keeping pins to clear state some pins are remaining high on boot up.

Please help on how to configure ePWM1A for high from zero to CAU and ePWM1B high for PRD to CAD. I tried this and the settings are shown below, but I'm not getting the desired output. Please let me know if there are any changes to be made or should I use up mode for ePWM.

Please tell me how should I keep PWM to low state on power ON. Even by pulling down pins and keeping pins to clear state some pins are remaining high on boot up.

Please help on how to configure ePWM1A for high from zero to CAU and ePWM1B high for PRD to CAD. I tried this and the settings are shown below, but I'm not getting the desired output. Please let me know if there are any changes to be made or should I use up mode for ePWM.

    // EPWM Module 1 config
    EPwm1Regs.TBPRD = 2647; // 17kHz PWM @ 90MHz
//    EPwm1Regs.CMPA.half.CMPA =2647/2;
    EPwm1Regs.TBPHS.half.TBPHS = 0; 
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

    EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1A
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    EPwm1Regs.AQCTLB.bit.PRD = AQ_SET;
    EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;

    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
    EPwm1Regs.DBFED = 10; // 
    EPwm1Regs.DBRED = 10; // 


        // Interrupt where we will change the Deadband
        EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
        EPwm1Regs.ETSEL.bit.INTEN = 1;                // Enable INT
        EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;           // Generate INT on 3rd event

                         // Disable EALLOW protected register access

        //SOC Generation Setting                            // ADC start of conversion on period
        EPwm1Regs.ETSEL.bit.SOCAEN  = 1;
        EPwm1Regs.ETSEL.bit.SOCASEL   = ET_CTR_PRD;
        EPwm1Regs.ETPS.bit.SOCAPRD  = ET_1ST;
        EPwm1Regs.ETSEL.bit.SOCBEN  = 1;
        EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTR_ZERO;
        EPwm1Regs.ETPS.bit.SOCBPRD  = ET_1ST;

// updating duty cycle in interrupt

interrupt void epwm1_isr(void)
{
EPwm1Regs.CMPA.half.CMPA = duty_cycle;
EPwm1Regs.CMPB = (duty_cycle);

// Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1;

// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

}

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

need is to generate PWM 1A with duty cycle variable and PWM 1B with same duty cycle shifted by 180 degrees for full bridge converters.

 Please help.

  • Ravi,

    For keeping the output low you will need a pull-down resistor...you should take a look at section 3.4.3 "Control Peripherals - PWM, CAP, QEP and Event Manager" of our Hardware Design Guidelines document. The excerpt below was take from the document.

    "

    at reset these GPIO pins are defined as input with the internal pullups enabled, except
    for the pins providing PWM output for which they are disabled. This condition remains for a short duration
    until the ports are initialized. Normally, there is no need for any external PU/PD resistor, unless it is
    mandatory for your schematic design.

    "

    For you PWM configuration question: Your code looks reasonable, what output do you see from the PWMs? How can you tell it is not working correctly?


    Regards,
    Cody 

  • Cody Watkins said:

    For you PWM configuration question: Your code looks reasonable, what output do you see from the PWMs? How can you tell it is not working correctly?

    Sir,

    The problem occurs when both rising and falling dead bands is enabled. Both ePWM1A and ePWM1B start at zero but I want ePWM1B from PRD i.e. 180 degree shift.

    For only rising or falling I do get the required.

    Please help

  • Ravi,

              Have no worry, this it possible. My guess is that you have a few configurations wrong in the DB sub-module.

    I ran a quick test, I started with the DeadBand example in controlSuite. I made a few modifications:

    1. I used up/down-count mode
    2. I added CMPB = (TBPRD-CMPA)
    3. For CMPA: ZRO= SET and CAU =CLEAR
    4. For CMPB: PRD= SET and CBD = CLEAR
    5. Changed the POLSEL to Active High
    6. Changed IN_MODE to accept 2 PWM signals from the AQ sub-module

    To make the pulses equal in duty i needed to use both CMPA and CMPB, if i only used CMPA then one signal would be the complement of the other ex. if A was 25% duty then B would be 75%.

    Take a look at the example and see if my modifications get you close to where you want to be.


    Regards,
    Cody