Tool/software: Code Composer Studio
Hello, Cottier
Thank you for your guidance.
We tested some registers of the ePWM module, including EPwmxRegs.TZFLG.all, EPwmxRges.TZCTL.all, EPwmxRges.DBCTL.all, EPwmxRges.AQCTL.all, EPwmxRges.AQCTLA.all, EPwmxRges.TBCTL.all, (x=1/2/3）.The values of these registers are all expected. During the test, we found that when the ePWM module is not working properly, some function calls are not executed, especially the FLASH program calls the function running in RAM, or the RAM program calls the function running in FLASH. Is it a CMD file error? The following is the CMD file. Please help to see if there is any error or inappropriateness.
// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define
#ifndef CLA_C
#define CLA_C
#endif //CLA_C
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0_1 : origin = 0x008000, length = 0x001000
RAMLS3_5 : origin = 0x009800, length = 0x001800
//RAMLS3 : origin = 0x009800, length = 0x000800
//RAMLS4 : origin = 0x00A000, length = 0x000800
//RAMLS5 : origin = 0x00A800, length = 0x000800
RAMGS14 : origin = 0x01A000, length = 0x001000
RAMGS15 : origin = 0x01B000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
//RAMLS0 : origin = 0x008000, length = 0x000800
//RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
//RAMLS3 : origin = 0x009800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12 : origin = 0x018000, length = 0x001000
RAMGS13 : origin = 0x019000, length = 0x001000
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHE PAGE = 0, ALIGN(4)
.pinit : > FLASHE, PAGE = 0, ALIGN(4)
.text : >> FLASHF PAGE = 0, ALIGN(4)
codestart : > BEGIN PAGE = 0, ALIGN(4)
ramfuncs : LOAD = FLASHD,
RUN = RAMLS0_1,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAMGS5 PAGE = 1
.esysmem : > RAMGS6 PAGE = 1
/* Initalized sections go in Flash */
.econst : > FLASHB PAGE = 0, ALIGN(4)
.switch : > FLASHB PAGE = 0, ALIGN(4)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
Filter_RegsFile : > RAMGS0, PAGE = 1
.sysmem : > RAMGS7, PAGE = 1
.cio : > RAMGS8, PAGE = 1
/* CLA specific sections */
Cla1Prog : LOAD = FLASHC,
RUN = RAMLS3_5,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0, ALIGN(4)
CLADataLS0 : > RAMLS2, PAGE=1
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
#ifdef __TI_COMPILER_VERSION
#if __TI_COMPILER_VERSION >= 15009000
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0_1,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#endif
#endif
/* The following section definition are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS2, PAGE = 1
.scratchpad : > RAMLS2, PAGE = 1
.bss_cla : > RAMLS2, PAGE = 1
.const_cla : LOAD = FLASHC,
RUN = RAMLS2,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
PAGE = 1
#endif //CLA_C
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
The following is PAGE 0 of the.MAP file:
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
PAGE 0:
RAMM0 00000122 000002de 00000000 000002de RWIX
RAMLS0_1 00008000 00001000 00000870 00000790 RWIX
RAMLS3_5 00009800 00001800 00001598 00000268 RWIX
RAMD0 0000b000 00000800 00000000 00000800 RWIX
RAMGS14 0001a000 00001000 00000000 00001000 RWIX
RAMGS15 0001b000 00001000 00000000 00001000 RWIX
DCSM_OTP_Z1_LINKPOINT 00078000 0000000c 00000000 0000000c RWIX
DCSM_OTP_Z1_PSWDLOCK 00078010 00000004 00000000 00000004 RWIX
DCSM_OTP_Z1_CRCLOCK 00078014 00000004 00000000 00000004 RWIX
DCSM_OTP_Z1_BOOTCTRL 0007801c 00000004 00000000 00000004 RWIX
DCSM_ZSEL_Z1_P0 00078020 00000010 00000000 00000010 RWIX
DCSM_OTP_Z2_LINKPOINT 00078200 0000000c 00000000 0000000c RWIX
DCSM_OTP_Z2_GPREG 0007820c 00000004 00000000 00000004 RWIX
DCSM_OTP_Z2_PSWDLOCK 00078210 00000004 00000000 00000004 RWIX
DCSM_OTP_Z2_CRCLOCK 00078214 00000004 00000000 00000004 RWIX
DCSM_OTP_Z2_BOOTCTRL 0007821c 00000004 00000000 00000004 RWIX
DCSM_ZSEL_Z2_P0 00078220 00000010 00000000 00000010 RWIX
BEGIN 00080000 00000002 00000002 00000000 RWIX
FLASHA 00080002 00001ffe 00000000 00001ffe RWIX
FLASHB 00082000 00002000 0000025d 00001da3 RWIX
FLASHC 00084000 00002000 00001598 00000a68 RWIX
FLASHD 00086000 00002000 00000870 00001790 RWIX
FLASHE 00088000 00008000 0000001a 00007fe6 RWIX
