Tool/software: Code Composer Studio
We use TMS320F28377S to control the three phase synchronous motor of elevator and ePWM1A/B-ePWM3A/B to generate three-phase SVPWM output. EPWM6A is used to output pulse signal to control elevator brake. SYSCLKOUT=120MHz. Call the following function to configure the ePWM module:
void SetPWM123(void) // setup ePWM1/2/3 modules for SVPWM
{ EPwm1Regs.TBCTL.bit.SYNCOSEL =0; /* Pass through*/
EPwm2Regs.TBCTL.bit.SYNCOSEL =0; /* Pass through*/
EPwm3Regs.TBCTL.bit.SYNCOSEL =0; /* Pass through*/
EPwm1Regs.TBCTL.bit.PHSEN =1; /* Allow each timer to be sync'ed*/
EPwm2Regs.TBCTL.bit.PHSEN =1; /* Allow each timer to be sync'ed*/
EPwm3Regs.TBCTL.bit.PHSEN =1; /* Allow each timer to be sync'ed*/
EPwm1Regs.TBPRD =2000; // set timer period,
EPwm2Regs.TBPRD =2000; // set timer period
EPwm3Regs.TBPRD =2000; // set timer period
EPwm1Regs.TBPHS.bit.TBPHS =0; // Phase is 0
EPwm2Regs.TBPHS.bit.TBPHS =0; // Phase is 0
EPwm3Regs.TBPHS.bit.TBPHS =0; // Phase is 0
EPwm1Regs.TBCTL.all =0xA08A; //0x2092;free run, count up when sync, TBCLK 30M,
EPwm2Regs.TBCTL.all =0xA08A; //0x2086;free run, count up when sync, TBCLK 30M
EPwm3Regs.TBCTL.all =0xA08A; //0x2086;free run, count up when sync, TBCLK 30M,
EPwm1Regs.CMPCTL.all =0; // load CMPA/B when CTR=0, shadow mode
EPwm2Regs.CMPCTL.all =0; // load CMPA/B when CTR=0, shadow mode
EPwm3Regs.CMPCTL.all =0; // load CMPA/B when CTR=0, shadow mode
EPwm1Regs.CMPA.bit.CMPA =200; // CMPA
EPwm2Regs.CMPA.bit.CMPA =200; // CMPA
EPwm3Regs.CMPA.bit.CMPA =200; // CMPA
EPwm1Regs.AQCTLA.all =0x61; // set wehn CAU, clear when CAD or CTR=0
EPwm2Regs.AQCTLA.all =0x61; // set wehn CAU, clear when CAD or CTR=0
EPwm3Regs.AQCTLA.all =0x61; // set wehn CAU, clear when CAD or CTR=0
EPwm1Regs.DBCTL.all =11; // enable deadband, active high complementary
EPwm2Regs.DBCTL.all =11; // enable deadband, active high complementary
EPwm3Regs.DBCTL.all =11; // enable deadband, active high complementary
EPwm1Regs.DBRED.all =60; // PWM rising-edge delay
EPwm1Regs.DBFED.all =60; // PWM falling-edge delay
EPwm2Regs.DBRED.all =60; // PWM rising-edge delay
EPwm2Regs.DBFED.all =60; // PWM falling-edge delay
EPwm3Regs.DBRED.all =60; // PWM rising-edge delay
EPwm3Regs.DBFED.all =60; // PWM falling-edge delay
EALLOW;
EPwm1Regs.TZCTL.all =10; // set trip zone signal will clear ePWM1A/B pin out low
EPwm2Regs.TZCTL.all =10; // set trip zone signal will clear ePWM1A/B pin out low
EPwm3Regs.TZCTL.all =10; // set trip zone signal will clear ePWM1A/B pin out low
EPwm1Regs.TZFRC.bit.OST =1; // force ePWM1A and ePWM1B pin output low
EPwm2Regs.TZFRC.bit.OST =1; // force ePWM2A and ePWM2B pin output low
EPwm3Regs.TZFRC.bit.OST =1; // force ePWM1A and ePWM3B pin output low
EDIS;
EPwm1Regs.TBCTR =0; // Clear counter
EPwm2Regs.TBCTR =0; // Clear counter
EPwm3Regs.TBCTR =0; // Clear counter
EPwm6Regs.TBCTL.all =0xA08A; // free run, count up when sync, TBCLK 30M
EPwm6Regs.TBPRD =12500; // Set timer period, 1.2k Hz
EPwm6Regs.AQCTLA.all =0x61;
EPwm6Regs.DBCTL.all =8; // disable deadband, active high complementary
EPwm6Regs.CMPA.bit.CMPA =10000; // CMPA
EPwm6Regs.TBCTR =0; // Clear counter
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
EPwm6Regs.TZCTL.all =2; // set trip zone signal will clear ePWM6A pin out low
EPwm4Regs.TZFRC.bit.OST =1; // force EPWM4A pin output low, not brake
EPwm6Regs.TZFRC.bit.OST =1; // force ePWM6A pin output low, not open lock
EDIS;
}
Invoke the following function to start the ePWM output:
void EPinPWM123(void) // enable ePWM1/2/3 pin output
{ EALLOW;
Cla1Regs.MICLR.all =0xFF; // clear all cla interrupt flag
Cla1Regs.MICLROVF.all =0xFF; // clear all cla interrupt overflow flag
Cla1Regs.MIER.all =0x81; // enable CLA interrupt 1,8, disable 7
EDIS;
AdcaRegs.ADCINTFLGCLR.all=15; // clear ADCAINT1-4
AdcaRegs.ADCINTOVFCLR.all=15; // clear ADCAINTOVFCLR1-4
EPwm1Regs.ETCLR.all =5; // // Clear EPWM1 INT, ADCA
EALLOW;
PieVectTable.EPWM1_INT =&epwm1_timer_isr;
EPwm1Regs.TZCLR.bit.OST =1; // enable ePWM1A and ePWM1B pin output
EPwm2Regs.TZCLR.bit.OST =1; // enable ePWM2A and ePWM2B pin output
EPwm3Regs.TZCLR.bit.OST =1; // enable ePWM1A and ePWM3B pin output
EPwm6Regs.TZCLR.bit.OST =1; // enable ePWM6A
EDIS;
EPwm1Regs.ETSEL.all =0x909; // SOCA when TBCTR =TBPRD, enable underflow
}
The values of EPwm1Regs.CMPA.bit.CMPA, EPwm2Regs.CMPA.bit.CMPA, and EPwm3Regs.CMPA.bit.CMPA are calculated and set in Cla1Task1 (void), and the SVPWM wave is output in ePWMxA/B.(x=1/2/3).
Call the following function to stop the PWM output:
void LPinPWM123(void) // force ePWM1/2/3 output low
{ EALLOW;
EPwm1Regs.TZCTL.all =10; // set trip zone signal will clear ePWM1A/B pin out low
EPwm2Regs.TZCTL.all =10; // set trip zone signal will clear ePWM1A/B pin out low
EPwm3Regs.TZCTL.all =10; // set trip zone signal will clear ePWM1A/B pin out low
EPwm6Regs.TZCTL.all =2; // set trip zone signal will clear ePWM1A/B pin out low
EPwm1Regs.TZFRC.bit.OST =1; // force ePWM1A and ePWM1B pin output low
EPwm2Regs.TZFRC.bit.OST =1; // force ePWM2A and ePWM2B pin output low
EPwm3Regs.TZFRC.bit.OST =1; // force ePWM1A and ePWM3B pin output low
EPwm3Regs.TZFRC.bit.OST =1; // force ePWM6A output low
EDIS;
}
Call the above function to start and stop PWM output for about 3~7 times (PWM module runs normally), and then start PWM output, regardless of the value of EPwmxRegs.CMPA.bit.CMPA, ePWMxA/B (x=1/2/3) output high resistance at the same time, or at the same time output high level, ePWM6A is always high resistance or high level. What's the reason?
We think the possible reason is that there is an out of range pointer writing operation in the program, and the EPwmxRegs.TZCTL or EPwmxRegs.TBCTL registers are erroneously modified. We checked all the codes carefully and found no such cases.
