TMS320F280049: CBC feature on F28004x Device

/* Example software demonstrating duty cycle matching with the EPWM and ECAP modules
 * This example requires 1 ECAP in APWM per EPWM module which requires the duty matching feature
 *
 * In this example, the EPWM ISR modifies CMPA to demonstrate the behavior of the
 * B channel pulse width as the A channel pulse width is changed. This is simulating a
 * CBC event for the purposes of this example.
 *
 * The ECAP is set to a 50% duty cycle with the same period as the PWM.
 * Whenever PWMA has a falling edge, the ECAP receives a SYNC and begins counting
 * at CTR=0. The falling edge of the ECAP causes a T2 event in the EPWM to create
 * a falling edge on EPWMB. This effectively creates a duty matching feature in the EPWM.
 *
 * In this example, ECAP1OUT is shown on GPIO5 for demonstration purposes only! An extra
 * pin is not required as it is routed directly to the EPWM through the EPWM X-BAR.
 *
 * Kris Parrent
 * May 26th, 2018
 * kris@realcoders.com
 */
//
// Included Files
//
#include "F28x_Project.h"

//
//  Function Prototypes
//
void InitECapAPWM(void);
void InitEPwm1Example(void);
interrupt void epwm1_isr(void);

//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    InitSysCtrl();

    EALLOW;
    ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0; // Set EPWMCLK = SYSCLK for this example. Your device should run at 100 MHz or less.
    EDIS;
//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
//    InitGpio();

//
// Enable PWM1, PWM2 and PWM3
//
    EALLOW;
    CpuSysRegs.PCLKCR2.bit.EPWM1=1;
    CpuSysRegs.PCLKCR3.bit.ECAP1 = 1;
    EDIS;

//
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F2837xD_EPwm.c file
//
    InitEPwm1Gpio();
    InitAPwm1Gpio();

    EALLOW;
    SyncSocRegs.SYNCSELECT.bit.ECAP1SYNCIN = 6; // ECAP1SYNCIN = EXTSYNCIN2 = INPUTXBAR6
    InputXbarRegs.INPUT6SELECT = 0;             // GPIO0 = EPWM1A
    GpioCtrlRegs.GPAINV.bit.GPIO0 = 1;          // Invert Input on GPIO0 (Sync chain is active high, want sync on falling edge)

    // Set ECAP1.OUT to TRIP4 on EPWM X-Bar
    EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 3; // ECAP1OUT
    EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1;   // Enable MUX0
    EDIS;
//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
    DINT;

//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
    InitPieVectTable();

    EALLOW;
    PieVectTable.EPWM1_INT = &epwm1_isr;
    EDIS;
//
// For this example, only initialize the ePWM
//
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;

    InitEPwm1Example();
    InitECapAPWM();

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;

//
// Step 4. User specific code, enable interrupts:
//
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//
    IER |= M_INT3;

//
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
//
    PieCtrlRegs.PIEIER3.bit.INTx1 = 1;

//
// Enable global Interrupts and higher priority real-time debug events:
//
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM


//
// Step 5. IDLE loop. Just sit and loop forever (optional):
//
    for(;;)
    {
        asm ("  NOP");
    }
}

interrupt void epwm1_isr()
{
    if(EPwm1Regs.CMPA.bit.CMPA != 499)
    {
        EPwm1Regs.CMPA.bit.CMPA += 100;
    }else
    {
        EPwm1Regs.CMPA.bit.CMPA = 99;
    }

    //
    // Clear INT flag for this timer
    //
    EPwm1Regs.ETCLR.bit.INT = 1;

    //
    // Acknowledge this interrupt to receive more interrupts from group 3
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
//
// InitEPwm1Example - Initialize EPWM1 values
//
void InitEPwm1Example()
{
    EALLOW;
   //
   // Setup TBCLK
   //
   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
   EPwm1Regs.TBPRD = 999;                     // Set timer period
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
   EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
   EPwm1Regs.TBCTR = 0x0000;                  // Clear counter
   EPwm1Regs.TBCTL.bit.SYNCOSEL = 2;          // Generate SYNCO on CMPB (falling edge of A channel)

   // Set PWM dividers to /1
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
   EPwm1Regs.TBCTL.bit.CLKDIV = 0;

   EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
   EPwm1Regs.ETSEL.bit.INTEN = 1;                // Enable INT
   EPwm1Regs.ETPS.bit.INTPRD = ET_3RD;           // Generate INT on 3rd event

   //
   // Setup shadow register load on ZERO
   //
   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

   //
   // Set Compare values
   //
   EPwm1Regs.CMPA.bit.CMPA = 499;     // Set compare A value
   EPwm1Regs.CMPB.bit.CMPB = 499;     // Set compare A value

   //
   // Set actions
   //
   EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;        // Set PWM1A on Zero
   EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;      // Clear PWM1A on event A,
                                             // up count

   EPwm1Regs.AQCTLB.bit.PRD = AQ_CLEAR;      // Set PWM1B on Zero
   EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;        // Clear PWM1B on event B,

   EPwm1Regs.AQTSRCSEL.bit.T2SEL = 3;        // DCBEVT2
   EPwm1Regs.AQCTLB2.bit.T2U = 1;            // Clear B channel on T2 event

   // Configure Digital Compare for ECAP1.OUT on TRIP4
   EPwm1Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 3; // DCBL = TRIP4
   EPwm1Regs.DCBCTL.bit.EVT1SRCSEL = 0;
   EPwm1Regs.TZDCSEL.bit.DCBEVT2 = 3;       // DCBEVT1 = DCBL low DCBH don't care
   EPwm1Regs.TZCTL.bit.DCBEVT2 = 3;         // Do nothing to EPWMB on DCBEVT2

   EDIS;
}

void InitECapAPWM()
{
    //
    // Setup APWM mode on CAP1, set period and compare registers
    //
       ECap1Regs.ECCTL2.bit.CAP_APWM = 1;       // Enable APWM mode
       ECap1Regs.ECCTL2.bit.APWMPOL = 0;        // Active high polarity
       ECap1Regs.ECCTL2.bit.SYNCI_EN = 1;       // Enable SYNCI
       ECap1Regs.CTRPHS = 0;
       ECap1Regs.CAP1 = 999;                    // Set Period value
       ECap1Regs.CAP2 = 487;                    // Set Compare value
                                                // This should be approximately 50% duty cycle
                                                // It is slightly shorter to account for propagation
                                                // and latch delays from the ECAP through EPWM
       ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1;      // Start counter

}

//
// End of file
//