F28M35H52C: ADC Source Impedance setup.

Hello Tommy,

I read the discussion on the two flollowing threads:

https://e2e.ti.com/support/microcontrollers/c2000/f/902/t/671517

https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/542665/1992904

It seems that the method to choose the external RC component is still the same for all microcontroller as long as the ADC equivalent circuit of the MCU is procided:

- Cext should have a minimum capacitance to be able to transfer charges to the Cmux and Csample capacitor (voltage on Csamp settles to within 1/4 LSB of the exact value) during the sampling time (sampling time can be setup by software);

- Rext should be lower than a maximum value to be able to recover the voltage of Cext between 2 ADC conversions.

I made calculations to setup the RC of my applcation with an Hercules microcontroler;

I found Cext min = 475nF (Cext min = 16383 * (16.10^-12 + 13.10^-12)) I choose Cext=680nF

I found Rext max = 9,4ohm (Rext max= 62.5µs /(9.7 *680nF).

I made some simulations and check that my values are correct to avoid the bump in settling time shown in picture Figure 6 of spna118b.pdf:

At page 20 of slyp166.pdf, TI advice to choose Cext=20*Csample where as in spna118b.pdf or on the TI forum, TI advice to choose Cext=16383*Csample (for 12bit ADC); This latter method seems to me more accurate.

My question is: Why slyp166.pdf advice to use only 20*Csample where as on latter application notes TI advice Cext=16383*Csample ?

Best regards,

JDM

JDM,

Both application notes are correct, but they are approaching the issue from two different use conditions.

The Cext=16383*Csample approach is for lower bandwidth signal sampling because of how slow the resulting time constant will be when using a very large Cext. This is a very simple and reliable approach where the role of Cext is to store energy when idle and then rapidly transfer charge to Csample within the sampling window. No signal buffering is needed as long as Cext has time to settle between samples.

The Cext=20*Csample approach is for higher bandwidth signal sampling. In this scenario, Cext is acting as an anti-aliasing filter rather than as a charge source. Cext is not large enough to fully charge Csample so the op-amp buffer assumes the role of charging Csample within the sampling window.

-Tommy

Hello Tommy,

thank you for your answer.

In my case, I will use an op-amp for level shifter and anti aliasing requirements. More over, I setup a low sample time (250ns) and the conversion rate will be 16kHz on a 8kHz input sinus signal with a 12-bit ADC.

With your explanation, It seems that I am in the second condition (slyp166.pdf). In this way, I need Cext min= 20*Csample.

In slyp166.pdf page 20, TI says:

"Once the C value is chosen, the R value can be found by noting that this RC filter must fully settle to the desired accuracy within the acquisition time of the converter."

What does TI mean by "acquisition time"; I use a TMS570LS0332 MCU; For the computation of Rext = tacq/(18*Cext), does tacq is:

• td(SH) (Delay time, sample and hold time),
• or td(C) (Delay time, conversion time),
• or td(SHC) (addition of the td(SH) and td(C)),
• or the duration between 2 conversions ?

In slyp166.pdf, Rext = tacq/(18*Cext) applies for a 16bit ADC. With a 12 bits ADC which time constant can I apply to keep a 50% margin?

Best regards.

JDM

JDM,

The acquisition time is when the Csample capacitor is exposed to the signal that you wish to sample.  I am not familiar with TMS570LS0332, but I would say that the td(SH) parameter is the acquisition time.

You should be able to apply the 16b ADC equation for selecting the RC cutoff to your 12b ADC without any modification.  It has more to do with anti-aliasing than with ADC precision.

-Tommy