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TMS320F28035: Question about using CLA assembly instruction

James Will
Prodigy 60 points
Part Number: TMS320F28035


HI,

My question is about this CLA assembly instruction 'MBCNDD'.

Typically, it is used like in this example:

MMOV32    MR0, @State
MCMPF32 MR0, #0.1 ;
MNOP
MNOP
MNOP
MBCNDD Skip1, NEQ

So, if State is not equal to 0.1, then it branches to 'Skip1'.

But I also saw code like this:

MMOV32    MR0, @_LED_is_on
MNOP
MNOP
MNOP
MBCNDD Skip1, NEQ

There is no comparison instruction used (MCMPF32) before check the condition of the branch instruction. 

Why is this code allowed? How does it work? What is affecting the flag?

Thanks,

  • 0
    TI__Mastermind 32655 points

    Hi James,

    Can you tell us where did you find the second code snippet?

    The compare instruction need not be immediately followed by the branch instruction. The branch instruction checks for the ZF flag set by the previous compare instruction

    For example:

    Regards,

    Veena

  • 0
    Expert 2520 points

    Hi,

    MMOV32 updates negative (NF) and zero (ZF) flags, so it automativally performs ==0, !=0, <0 and >=0 compares. Since no 'F' letter in instruction name, I would expect NF and ZF be updated according to integer compare against zero, but in user manual

    MMOV32 MRa, mem32 {, CNDF} Conditional 32-Bit Move

    ...

    if(CNDF == UNCF)

    {

    NF = MRa(31);

    ZF = 0;

    if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

    }

    Looks like it is floating point compare against zero, without support for FP gradual underflow. Pseudocode checks exponent of single precision number (MRa(30:23)), and if it's zero then number is treated as zero.

    I'd like to check if it's the case. I guess your _LED_is_on variable is integer, isn't it? If yes, then either documentation is wrong or compiled code is wrong.

    Edward

  • 0 in reply to EK
    TI__Mastermind 32655 points

    Edward,

    I doubt whether the MMOV32 instruction updates the NF and ZF flags. I agree if it is a conditional mov instruction. In the code snippet James shared, it is a mov instruction without condition. I believe, it does not update the any of the flags in MSTF register

    Regards,
    Veena

  • 0 in reply to Veena Kamath
    Expert 2520 points

    Hi Veena,

    Just tried myself. 28337 CLA documentation is correct, MMOV32 updates ZF and NF according to FP compare against 0.0 and treating nonzero numbers with zero exponent as zero.

    Your previous message needs to be corrected

    • The branch instruction checks for the ZF flag set by the previous compare instruction

    set previously, not by previous compare instruction. MABSF32 and others do also update ZF and NF flags.

    Compiler efficiently uses this feature

    volatile float lstatus;

    192               if(lstatus < 0)
    0000a978:   73C0804C    MMOV32     MR0, @0x804c, UNCF
    0000a97a:   7FA00000    MNOP      
    0000a97c:   7FA00000    MNOP      
    0000a97e:   7FA00000    MNOP      
    0000a980:   79830014    MBCNDD     0x14, GEQ
    0000a982:   7FA00000    MNOP      
    0000a984:   7FA00000    MNOP      
    0000a986:   7FA00000    MNOP      
    193                   lstatus++;
    0000a988:   73C0804C    MMOV32     MR0, @0x804c, UNCF
    0000a98a:   77C03F80    MADDF32    MR0, #0x3f80, MR0
    0000a98c:   74C0804C    MMOV32     @0x804c, MR0
    0000a98e:   7FA00000    MNOP      
    0000a990:   7FA00000    MNOP      
    0000a992:   7FA00000    MNOP      
    194               if(lstatus >= 0)
              C$L5:
    0000a994:   73C0804C    MMOV32     MR0, @0x804c, UNCF
    0000a996:   7FA00000    MNOP      
    0000a998:   7FA00000    MNOP      
    0000a99a:   7FA00000    MNOP      
    0000a99c:   79840014    MBCNDD     0x14, LT
    0000a99e:   7FA00000    MNOP      
    0000a9a0:   7FA00000    MNOP      
    0000a9a2:   7FA00000    MNOP      
    195                   lstatus+=2;
    0000a9a4:   73C0804C    MMOV32     MR0, @0x804c, UNCF
    0000a9a6:   77C04000    MADDF32    MR0, #0x4000, MR0
    0000a9a8:   74C0804C    MMOV32     @0x804c, MR0
    0000a9aa:   7FA00000    MNOP      
    0000a9ac:   7FA00000    MNOP      
    0000a9ae:   7FA00000    MNOP      
    196               if(lstatus != 0)
              C$L6:
    0000a9b0:   73C0804C    MMOV32     MR0, @0x804c, UNCF
    0000a9b2:   7FA00000    MNOP      
    0000a9b4:   7FA00000    MNOP      
    0000a9b6:   7FA00000    MNOP      
    0000a9b8:   79810014    MBCNDD     0x14, EQ
    0000a9ba:   7FA00000    MNOP      
    0000a9bc:   7FA00000    MNOP      
    0000a9be:   7FA00000    MNOP      
    197                   lstatus+=3;
    0000a9c0:   73C0804C    MMOV32     MR0, @0x804c, UNCF
    0000a9c2:   77C04040    MADDF32    MR0, #0x4040, MR0
    0000a9c4:   74C0804C    MMOV32     @0x804c, MR0
    0000a9c6:   7FA00000    MNOP      
    0000a9c8:   7FA00000    MNOP      
    0000a9ca:   7FA00000    MNOP      
    198               if(lstatus == 0)
              C$L7:
    0000a9cc:   73C0804C    MMOV32     MR0, @0x804c, UNCF
    0000a9ce:   7FA00000    MNOP      
    0000a9d0:   7FA00000    MNOP      
    0000a9d2:   7FA00000    MNOP      
    0000a9d4:   7980000E    MBCNDD     0xe, NEQ
    0000a9d6:   7FA00000    MNOP      
    0000a9d8:   7FA00000    MNOP      
    0000a9da:   7FA00000    MNOP      
    199                   lstatus+=4;
    0000a9dc:   73C0804C    MMOV32     MR0, @0x804c, UNCF
    0000a9de:   77C04080    MADDF32    MR0, #0x4080, MR0
    0000a9e0:   74C0804C    MMOV32     @0x804c, MR0


    Edward

  • 0 in reply to EK
    TI__Mastermind 32995 points
    Edward, James,

    Many instructions in the CLA, including the MMOV32 instruction, update the flags. The MMOV32 instruction updates the ZF and NF flags. Therefore, in the second example the branch will or will not occur based on the latest completed update to the flags, i.e. the MMOV32 instruciton.

    You can see this in the TRM.

    Edward, I believe your understanding is correct.

    Hope this help.

    Regards,
    sal
  • 0 in reply to Sal Pezzino
    Prodigy 60 points
    Thanks to everyone for your help.

    James