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In my code, DSP is the master and FPGA is the slave. Dsp sends 3 words to FPGA which returns the same value bit by bit. If the sent data matches with the received data the DSP continues operation or else transmit 0 so that the FPGA doesn't output any PWM signal generated from the received data from DSP.
My main.c looks like the code shown below:
#include "DSP281x_Device.h" // DSP281x Headerfile Include File #include "DSP281x_Examples.h" // DSP281x Examples Include File // Prototype statements for functions found within this file. interrupt void eva_timer1_isr(void); interrupt void eva_timer1_count_isr(void); void InitallRegs(void); // Global counts used in this example void main(void) { Uint16 i; Page1.sdata[0]=0x0A05; Page1.sdata[1]=0xB004; Page1.sdata[2]=0x0C03; InitallRegs(); InitPieVectTable(); EALLOW; // This is needed to write to EALLOW protected registers PieVectTable.T1UFINT = &eva_timer1_isr; EDIS; // This is needed to disable write to EALLOW protected registers // Step 6. IDLE loop. Just sit and loop forever: for(;;) { for(;;) { if (Page1.intflag==1) { Page1.intflag=0; break; } } if (Page1.spi_flag==0) { for(i= 0; i < 3; i++) { SpiaRegs.SPITXBUF=Page1.sdata[i]; } while(SpiaRegs.SPIFFRX.bit.RXFFST !=3) { } for(i= 0; i < 3; i++) { Page1.rdata[i]=SpiaRegs.SPIRXBUF; } for(i= 0; i < 3; i++) { if (Page1.rdata[i]!=Page1.sdata[i]) { Page1.spi_flag=1; //Page1.sdata[i]=Page1.rdata[i]; } } } else { for(i= 0; i < 3; i++) { Page1.sdata[i]=0x0000;//Page1.rdata[i];// SpiaRegs.SPITXBUF=Page1.sdata[i]; } } //------------------------------------------------------------------- if (Page1.spi_flag==0) { control(); } //------------------------------------------------------------------------- interrupt void eva_timer1_isr(void) { Page1.intflag=1; EvaRegs.EVAIFRA.bit.T1UFINT=1; // Acknowledge interrupt to receive more interrupts from PIE group 2 PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; DINT; EvaRegs.EVAIMRA.all=0; EvaRegs.EVAIMRA.bit.T1UFINT=1; PieCtrlRegs.PIEIER2.all=0; //disable underflow interrupt and enable T1 count interrupt PieCtrlRegs.PIEIER2.all = M_INT6;//M_INT4 EINT; }
And my initialisation of registers looks like this. All interrupts are disabled.
//SPI Initialisation // Interrupts are disabled and as such no Tx or Rx INTLVL bits are to be set SpiaRegs.SPICCR.bit.SPISWRESET=0; // Software Reset SPI SpiaRegs.SPICCR.all=0x000F; //send 16-bits character, Loopback mode enabled SpiaRegs.SPICTL.all=0x0006; //Interrupt disabled, Master mode, TX enabled, Clock Phase set to 0 SpiaRegs.SPISTS.all=0x0000; // Status Register : Read Only SpiaRegs.SPIBRR=0x0027;//0x0027 // Baud rate=27=>1.5 MHz SpiaRegs.SPIFFTX.all=0xC040; // resume SPI FIFO Tx or Rx, (Enhancements enabled), Reset FIFO Tx pointer to 0, TXINT flag is cleared SpiaRegs.SPIFFRX.all=0x004F; // Reset FIFO Rx pointer to 0, RXINT flag is cleared SpiaRegs.SPIFFCT.all=0x0000; //FIFO delay between two consecutive words set to 0 SPICLK cycles SpiaRegs.SPIPRI.all=0x0010; //FREE run : continue SPI operatio irrespective of suspend SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SPI communication SpiaRegs.SPIFFTX.bit.TXFIFO=1; // Re-enable FIFO Tx SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;// Re-enable FIFO Rx Page1.spi_flag=0;
Is there any problem with the reading of RXBUF because the code seems to work fine for loopback mode. Is there any better way to handle the reading of RXBUF?
I cannot read back the expected values. The DSP master transmits and FPGA slave receives at rising clk edge while the DSP receives and FPGA transmits at falling clk edge.
Now that I have looked into the received data on the oscilloscope by outputting the rdata through the sdata whenever the spi_flag gets high, it looked like the slave FPGA might be delaying the data transfer on the falling edge of the spiclk and so the DSP was reading the data on the next falling clk edge. So, apparently, the received data, in essence, might be right-shifted by 1 bit and so that might be a cause of the mismatch as I could see the transmitted data to be right-shifted.
If that is the case, can I left shift the entire SPIRXBUF by a bit like the following and then read it into the rdata array to check against the sdata the master DSP is sending? Because initially, I thought that there was a problem with the reading methodology of the SPIRXBUF which I still think might be a problem because I dont understand how does the RXBUF know which word it has to output to rdata and if the checking of the RXFFST is the only way around it.
while(SpiaRegs.SPIFFRX.bit.RXFFST !=3) { } SpiaRegs.SPIRXBUF=(SpiaRegs.SPIRXBUF<<1)|(some lost dummy bit);// Is this allowed??? for(i= 0; i < 3; i++) { Page1.rdata[i]=SpiaRegs.SPIRXBUF; }
By doing so, I intend to check if the data integrity is maintained, excluding the 1 bit which might be possibly lost in transmission. So, is the syntax correct?
Anyways, the GPIO configuration is set for the GPIOFMUX pins to act as SPI pins. So, I think that's correct.
Any progress on resolving this issue?
Edit: Since I haven't heard back from you, I'm going to assume you resolved the issue and close the thread. Feel free to comment and reopen if you need additional help though.
Whitney