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Quick power cycle of LF2407A

Andy Chernock
Intellectual 740 points

I have an engineer that is seeing issues when he quickly cycles power on the LF2407A.

Summary:  Upon power cycling, if power is reapplied while Vcc drops between ~100mV and ~200mV, the ‘LF2407A comes up into an unknown state.  At any other voltage level or when reset is applied, the ‘LF2407A works as expected. 

We have checked the errata and noticed the point made about the internal oscillator, but this has been checked (1M resistor has been added) and does not appear to be the problem.

I have much more information regarding the testing and a more detailed description of the problem if you wish.

Any other ideas??.

  • 0
    TI__Mastermind 18130 points

    Andy,

    There is no specific mention of power/reset sequencing in the datasheet, so this does sound like unexpected behavior. I am checking with the product group into this issue further.

    In the meantime, you mentioned that you have a more detailed description of the problem. Would you please add this to the forum thread so we can have as much context as possible? A description of the 'unknown state' would be nice if you have one.

  • 0 in reply to TimHarron
    Intellectual 740 points

    Thanks Tim...the customer is currently determining if the internal weak pull-ups/downs on the Boot Mode pins are weak enough leave the boot pins in an unexpected state during power cycling.

    This is the initial issue sent to me from the customer:

    I’ll start off by saying this is in a fairly mature design that is in production and it only happens under some very precise conditions, which I will explain.  Please keep this in mind as this is NOT a new development effort or our first time trying to bring up this processor.

     

    We are seeing an issue during “quick” power-cycles (and I will explain quick.)  We do not see any issue with “cold” power-on (when all supplies are completely discharged.)  The issue appears to be that the processor is not properly resetting or executing startup code during the failure mode.  The SCI output (which we use for serial communication with another board in the system) sends out an unknown message at what appears to be at a very slow baud rate.  By design, NO messages are to be transmitted until the other board initiates communication.  When the other board does initiate comm, the response is either unknown or not at all.  The failing processor still responds to incoming switch closures (which it is responsible for monitoring) as if it is running the code normally.

     

    Here is a description of the process to induce the failure.

     

    1) Monitor the 3.3V power rail which powers the LF2407 VDD and VDDO pins, and the SCI TX pin.

    2) Turn power off.  3.3V discharge rate is very slow due to minimum system loading.

    3) Wait until the 3.3V decays to under ~200mV but still above ~100mV.  This takes about 4 seconds (but this time is from memory.)

    4) Turn power back on.

    5) Almost immediately, some toggling occurs on the SCI TX pin.  The rate is very slow and system communication is frozen.

     

    I will note we DO have a reset controller on the LF2407 RS- pin that is working properly.  It holds RS- low for 250ms after the 3.3V rail is stable.  It IS working correctly.  The controller chip has a Manual Reset (MR) input which is not used normally.  However, during troubleshooting, we tried issuing a manual reset after observing the failure mode and comm was immediately restored.

     

    I will also note if you let the power rail fall below ~100mV (to even about 90mV) and then cycle power the failure mode is NOT observed.  Also, if you cycle power before the 3.3V rail falls below ~200mV the failure mode is NOT observed.  (I’m saying ~100mV and ~200mV because I don’t know exactly; HOWEVER, we do have cursors on our o-scope that show exactly where the window is and they appear to be close to those values I’m stating.)

     

    We are working to put together some test code to see if indeed the processor is not running through the startup code as desired.  Let me know if you any ideas or if some similar problems have been observed.