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Tool/software: Code Composer Studio
Hi,
I'm trying to use High resolution Period and Phase function for multi-phase digital power application.
When I asked to our FAE about High resolution function, they introduced following threads.
In these threads and example, access to " TRREM" register are found instead of access to "TBPHSHR".
There is little information about "TRREM" register in reference manual.
Could you explain the detail about "TRREM" register?
I’m attaching current EPWM initialization code for open control test without using TRREM register.
There is some jittering at slave phase waveform when TBPRDHR or TBPHSHR is not zero.
/* * EPWM.c * * Created on: 2018/07/10 * Author: onishi */ #include "EPWM_init.h" #include "f28004x_device.h" #include "driverlib.h" #include "device.h" // // initEPWM - Function to configure ePWM1 to generate the SOC. // void Initialize_EPWM1() { // // Set-up TBCLK // EPWM_setTimeBasePeriod(EPWM1_BASE, 20000); // EPwm4Regs.TBPRD = 20000; // Time Base Period Register //EPWM_setPhaseShift(EPWM1_BASE, 0U); EPWM_setTimeBaseCounter(EPWM1_BASE, 0U); // EPwm4Regs.TBCTL.bit.CTRMODE = 0; // Counter Mode // // Freeze the counter // EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_STOP_FREEZE); // // Set up counter mode // EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_UP_DOWN); //EPWM_enablePhaseShiftLoad(EPWM1_BASE); EPWM_disablePhaseShiftLoad(EPWM1_BASE); EPWM_setClockPrescaler(EPWM1_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); //Sync signal Output is at Counter ZERO. EPWM_setSyncOutPulseMode(EPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN); // EPwm4Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select // // Set up shadowing // // EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, // EPWM_COMP_LOAD_ON_CNTR_ZERO); // EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE, EPWM_COUNTER_COMPARE_B, // EPWM_COMP_LOAD_ON_CNTR_ZERO); // // Set actions // EPWM_setActionQualifierAction(EPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); //Set Period load mode. EPWM_setPeriodLoadMode(EPWM1_BASE, EPWM_PERIOD_SHADOW_LOAD); EPWM_selectPeriodLoadEvent(EPWM1_BASE, EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO); EPWM_setActionQualifierShadowLoadMode(EPWM1_BASE, EPWM_ACTION_QUALIFIER_A, EPWM_AQ_LOAD_ON_CNTR_ZERO); // EPwm4Regs.AQCTL.bit.SHDWAQAMODE = 1; // set shadow mode // EPwm4Regs.AQCTL.bit.LDAQASYNC = 0; // set shadow mode EPWM_setActionQualifierShadowLoadMode(EPWM1_BASE, EPWM_ACTION_QUALIFIER_B, EPWM_AQ_LOAD_ON_CNTR_ZERO); // EPwm4Regs.AQCTL.bit.SHDWAQBMODE = 1; // set shadow mode // EPwm4Regs.AQCTL.bit.LDAQBSYNC = 0; // set shadow mode EPWM_setActionQualifierContSWForceShadowMode(EPWM1_BASE, EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierContSWForceShadowMode(EPWM1_BASE, EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO); // // Set Compare values // EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, 0); EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_B, 0); EPWM_setDeadBandCounterClock(EPWM1_BASE,EPWM_DB_COUNTER_CLOCK_HALF_CYCLE); EPWM_setRisingEdgeDelayCount(EPWM1_BASE, 80); EPWM_setFallingEdgeDelayCount(EPWM1_BASE, 80); //OUT mode EPWM_setDeadBandDelayMode(EPWM1_BASE, EPWM_DB_RED, true); EPWM_setDeadBandDelayMode(EPWM1_BASE, EPWM_DB_FED, true); //IN_MODE EPWM_setRisingEdgeDeadBandDelayInput(EPWM1_BASE, EPWM_DB_INPUT_EPWMA); EPWM_setFallingEdgeDeadBandDelayInput(EPWM1_BASE, EPWM_DB_INPUT_EPWMA); EPWM_setDeadBandDelayPolarity(EPWM1_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH); // xB is inverted EPWM_setDeadBandDelayPolarity(EPWM1_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW); //PWM output is not swapped. EPWM_setDeadBandOutputSwapMode(EPWM1_BASE, EPWM_DB_OUTPUT_A,0); EPWM_setDeadBandOutputSwapMode(EPWM1_BASE, EPWM_DB_OUTPUT_B,0); // // // // //EPWM_setADCTriggerSource(EPWM1_BASE,EPWM_SOC_A,EPWM_SOC_TBCTR_ZERO); //EPWM_setADCTriggerSource(EPWM1_BASE, EPWM_SOC_B, EPWM_SOC_DCxEVT1); /* Generate pulse on 1st even*/ //EPWM_setADCTriggerEventPrescale(EPWM1_BASE, EPWM_SOC_A, 1); //EPWM_setADCTriggerEventPrescale(EPWM1_BASE, EPWM_SOC_B, 1); /* Enable SOC on A group*/ //EPWM_enableADCTrigger(EPWM1_BASE, EPWM_SOC_A); /* Enable SOC on B group*/ // EPWM_enableADCTrigger(EPWM1_BASE, EPWM_SOC_B); // EPWM_enableGlobalLoadRegisters( // EPWM1_BASE, // EPWM_GL_REGISTER_AQCTLA_AQCTLA2 | // EPWM_GL_REGISTER_AQCTLB_AQCTLB2 | EPWM_GL_REGISTER_TBPRD_TBPRDHR // | EPWM_GL_REGISTER_CMPA_CMPAHR // | EPWM_GL_REGISTER_CMPB_CMPBHR); EPWM_enableGlobalLoadRegisters( EPWM1_BASE, EPWM_GL_REGISTER_AQCTLA_AQCTLA2 | EPWM_GL_REGISTER_AQCTLB_AQCTLB2); EPWM_setGlobalLoadEventPrescale(EPWM1_BASE, 1); EPWM_setGlobalLoadTrigger(EPWM1_BASE, EPWM_GL_LOAD_PULSE_GLOBAL_FORCE); EPWM_enableGlobalLoadOneShotMode(EPWM1_BASE); EPWM_enableGlobalLoad(EPWM1_BASE); /* EPWM_enableTripZoneSignals(EPWM1_BASE, EPWM_TZ_SIGNAL_OSHT1 | EPWM_TZ_SIGNAL_OSHT2); EPWM_setTripZoneAction(EPWM1_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(EPWM1_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(EPWM1_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(EPWM1_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(EPWM1_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(EPWM1_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE); EPWM_disableTripZoneInterrupt( EPWM1_BASE, EPWM_TZ_INTERRUPT_CBC | EPWM_TZ_INTERRUPT_OST | EPWM_TZ_INTERRUPT_DCAEVT1 | EPWM_TZ_INTERRUPT_DCAEVT2 | EPWM_TZ_INTERRUPT_DCBEVT1 | EPWM_TZ_INTERRUPT_DCBEVT2); EPWM_enableTripZoneInterrupt(EPWM1_BASE, EPWM_TZ_INTERRUPT_OST); */ EPWM_disableDigitalCompareSyncEvent(EPWM1_BASE, EPWM_DC_MODULE_A); EPWM_setDigitalCompareEventSource(EPWM1_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM1_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // DCAEVT1 Force Sync Signal EPWM_setDigitalCompareEventSource(EPWM1_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM1_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0; // DCAEVT2 Force Sync Signal EPWM_enableDigitalCompareADCTrigger(EPWM1_BASE, EPWM_DC_MODULE_A); EPWM_enableDigitalCompareSyncEvent(EPWM1_BASE, EPWM_DC_MODULE_B); EPWM_setDigitalCompareEventSource(EPWM1_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM1_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // DCAEVT1 Force Sync Signal EPWM_setDigitalCompareEventSource(EPWM1_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM1_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0; // DCAEVT2 Force Sync Signal EPWM_enableDigitalCompareADCTrigger(EPWM1_BASE, EPWM_DC_MODULE_B); EPWM_selectDigitalCompareTripInput(EPWM1_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH); EPWM_selectDigitalCompareTripInput(EPWM1_BASE, EPWM_DC_TRIP_TRIPIN2, EPWM_DC_TYPE_DCAL); EPWM_selectDigitalCompareTripInput(EPWM1_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH); EPWM_selectDigitalCompareTripInput(EPWM1_BASE, EPWM_DC_TRIP_TRIPIN2, EPWM_DC_TYPE_DCBL); EPWM_setTripZoneDigitalCompareEventCondition(EPWM1_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH); EPWM_setTripZoneDigitalCompareEventCondition(EPWM1_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DC_DISABLED); EPWM_setTripZoneDigitalCompareEventCondition(EPWM1_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH); EPWM_setTripZoneDigitalCompareEventCondition(EPWM1_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DC_DISABLED); EPWM_disableDigitalCompareBlankingWindow(EPWM1_BASE); EPWM_disableDigitalCompareWindowInverseMode(EPWM1_BASE); //EPWM_setDigitalCompareBlankingEvent(EPWM1_BASE,EPWM_DC_WINDOW_START_TBCTR_ZERO); //EPWM_setDigitalCompareFilterInput(EPWM1_BASE, EPWM_DC_WINDOW_SOURCE_DCAEVT1); EPWM_setDigitalCompareWindowOffset(EPWM1_BASE, 0); EPWM_setDigitalCompareWindowLength(EPWM1_BASE, 0); EPWM_disableDigitalCompareCounterCapture(EPWM1_BASE); //driverlib bugs? /* HRPWM_setDeadbandMEPEdgeSelect(EPWM1_BASE, HRPWM_DB_MEP_CTRL_RED_FED); HRPWM_setMEPControlMode(EPWM1_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_setMEPControlMode(EPWM1_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_setCounterCompareShadowLoadEvent(EPWM1_BASE, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_enablePeriodControl(EPWM1_BASE); HRPWM_enableAutoConversion(EPWM1_BASE); HRPWM_disablePhaseShiftLoad(EPWM1_BASE); */ EALLOW; EPwm1Regs.HRCNFG.all = 0x0; EPwm1Regs.HRCNFG.bit.EDGMODE = 3; // MEP control on both edges EPwm1Regs.HRCNFG.bit.EDGMODEB = 3; // MEP control on both edges EPwm1Regs.HRCNFG.bit.CTLMODE = 0; EPwm1Regs.HRCNFG.bit.CTLMODEB = 0; EPwm1Regs.HRCNFG.bit.HRLOAD = 0; //Update at Zero EPwm1Regs.HRCNFG.bit.AUTOCONV = 1; // Enable auto-conversion logic EPwm1Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control. EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // TBPHSHR Load Enable EDIS; HRPWM_setOutputSwapMode(EPWM1_BASE,false);// not swapped; HRPWM_setChannelBOutputPath(EPWM1_BASE,HRPWM_OUTPUT_ON_B_NORMAL);// not swapped; // // Interrupt where we will change the Compare Values // Select INT on Time base counter zero event, // Enable INT, generate INT on 3rd event // EPWM_setInterruptSource(EPWM1_BASE, EPWM_INT_TBCTR_ZERO); /* Generate Interrupt on 1st even*/ EPWM_setInterruptEventCount(EPWM1_BASE, 2U); EPWM_enableInterrupt(EPWM1_BASE); } void Initialize_EPWM2() { // // Set-up TBCLK // EPWM_setTimeBasePeriod(EPWM2_BASE, 20000); // EPwm4Regs.TBPRD = 20000; // Time Base Period Register //EPWM_setPhaseShift(EPWM2_BASE, 0U); EPWM_setTimeBaseCounter(EPWM2_BASE, 0U); // EPwm4Regs.TBCTL.bit.CTRMODE = 0; // Counter Mode // // Freeze the counter // EPWM_setTimeBaseCounterMode(EPWM2_BASE, EPWM_COUNTER_MODE_STOP_FREEZE); // // Set up counter mode // EPWM_setTimeBaseCounterMode(EPWM2_BASE, EPWM_COUNTER_MODE_UP_DOWN); EPWM_enablePhaseShiftLoad(EPWM2_BASE); EPWM_setClockPrescaler(EPWM2_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); //Sync signal Output is at Counter ZERO. EPWM_setSyncOutPulseMode(EPWM2_BASE, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN); // EPwm4Regs.TBCTL.bit.SYNCOSEL = 0; // Sync Output Select EPWM_selectPeriodLoadEvent(EPWM2_BASE,EPWM_SHADOW_LOAD_MODE_SYNC); // (*ePWM[2]).TBCTL2.bit.PRDLDSYNC = 2; // Shadow to Active when SYC received // // Set up shadowing // // EPWM_setCounterCompareShadowLoadMode(EPWM2_BASE, EPWM_COUNTER_COMPARE_A, // EPWM_COMP_LOAD_ON_CNTR_ZERO); // EPWM_setCounterCompareShadowLoadMode(EPWM2_BASE, EPWM_COUNTER_COMPARE_B, // EPWM_COMP_LOAD_ON_CNTR_ZERO); // // Set actions // EPWM_setActionQualifierAction(EPWM2_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM2_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM2_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM2_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); //Set Period load mode. EPWM_setPeriodLoadMode(EPWM2_BASE, EPWM_PERIOD_SHADOW_LOAD); EPWM_selectPeriodLoadEvent(EPWM2_BASE, EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO); EPWM_setActionQualifierShadowLoadMode(EPWM2_BASE, EPWM_ACTION_QUALIFIER_A, EPWM_AQ_LOAD_ON_CNTR_ZERO); // EPwm4Regs.AQCTL.bit.SHDWAQAMODE = 1; // set shadow mode // EPwm4Regs.AQCTL.bit.LDAQASYNC = 0; // set shadow mode EPWM_setActionQualifierShadowLoadMode(EPWM2_BASE, EPWM_ACTION_QUALIFIER_B, EPWM_AQ_LOAD_ON_CNTR_ZERO); // EPwm4Regs.AQCTL.bit.SHDWAQBMODE = 1; // set shadow mode // EPwm4Regs.AQCTL.bit.LDAQBSYNC = 0; // set shadow mode EPWM_setActionQualifierContSWForceShadowMode(EPWM2_BASE, EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierContSWForceShadowMode(EPWM2_BASE, EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO); /* EPWM_setActionQualifierT1TriggerSource( EPWM2_BASE,EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1); // EPwm4Regs.AQTSRCSEL.bit.T1SEL = 2; EPWM_setActionQualifierT2TriggerSource( EPWM2_BASE,EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1); // EPwm4Regs.AQTSRCSEL.bit.T2SEL = 0; */ // // Set Compare values // EPWM_setCounterCompareValue(EPWM2_BASE, EPWM_COUNTER_COMPARE_A, 0); EPWM_setCounterCompareValue(EPWM2_BASE, EPWM_COUNTER_COMPARE_B, 0); EPWM_setDeadBandCounterClock(EPWM2_BASE,EPWM_DB_COUNTER_CLOCK_HALF_CYCLE); EPWM_setRisingEdgeDelayCount(EPWM2_BASE, 80); EPWM_setFallingEdgeDelayCount(EPWM2_BASE, 80); //OUT mode EPWM_setDeadBandDelayMode(EPWM2_BASE, EPWM_DB_RED, true); EPWM_setDeadBandDelayMode(EPWM2_BASE, EPWM_DB_FED, true); //IN_MODE EPWM_setRisingEdgeDeadBandDelayInput(EPWM2_BASE, EPWM_DB_INPUT_EPWMA); EPWM_setFallingEdgeDeadBandDelayInput(EPWM2_BASE, EPWM_DB_INPUT_EPWMA); EPWM_setDeadBandDelayPolarity(EPWM2_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH); // xB is inverted EPWM_setDeadBandDelayPolarity(EPWM2_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW); //PWM output is not swapped. EPWM_setDeadBandOutputSwapMode(EPWM2_BASE, EPWM_DB_OUTPUT_A,0); EPWM_setDeadBandOutputSwapMode(EPWM2_BASE, EPWM_DB_OUTPUT_B,0); // // // // //EPWM_setADCTriggerSource(EPWM2_BASE,EPWM_SOC_A,EPWM_SOC_TBCTR_ZERO); //EPWM_setADCTriggerSource(EPWM2_BASE, EPWM_SOC_B, EPWM_SOC_DCxEVT1); /* Generate pulse on 1st even*/ //EPWM_setADCTriggerEventPrescale(EPWM2_BASE, EPWM_SOC_A, 1); //EPWM_setADCTriggerEventPrescale(EPWM2_BASE, EPWM_SOC_B, 1); /* Enable SOC on A group*/ //EPWM_enableADCTrigger(EPWM2_BASE, EPWM_SOC_A); /* Enable SOC on B group*/ // EPWM_enableADCTrigger(EPWM2_BASE, EPWM_SOC_B); EPWM_enableGlobalLoadRegisters( EPWM2_BASE, EPWM_GL_REGISTER_AQCTLA_AQCTLA2 | EPWM_GL_REGISTER_AQCTLB_AQCTLB2 | EPWM_GL_REGISTER_TBPRD_TBPRDHR | EPWM_GL_REGISTER_CMPA_CMPAHR | EPWM_GL_REGISTER_CMPB_CMPBHR); EPWM_setGlobalLoadEventPrescale(EPWM2_BASE, 1); EPWM_setGlobalLoadTrigger(EPWM2_BASE, EPWM_GL_LOAD_PULSE_GLOBAL_FORCE); EPWM_enableGlobalLoadOneShotMode(EPWM2_BASE); EPWM_enableGlobalLoad(EPWM2_BASE); /* EPWM_enableTripZoneSignals(EPWM2_BASE, EPWM_TZ_SIGNAL_OSHT1 | EPWM_TZ_SIGNAL_OSHT2); EPWM_setTripZoneAction(EPWM2_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(EPWM2_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(EPWM2_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(EPWM2_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(EPWM2_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(EPWM2_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE); EPWM_disableTripZoneInterrupt( EPWM2_BASE, EPWM_TZ_INTERRUPT_CBC | EPWM_TZ_INTERRUPT_OST | EPWM_TZ_INTERRUPT_DCAEVT1 | EPWM_TZ_INTERRUPT_DCAEVT2 | EPWM_TZ_INTERRUPT_DCBEVT1 | EPWM_TZ_INTERRUPT_DCBEVT2); EPWM_enableTripZoneInterrupt(EPWM2_BASE, EPWM_TZ_INTERRUPT_OST); */ EPWM_disableDigitalCompareSyncEvent(EPWM2_BASE, EPWM_DC_MODULE_A); EPWM_setDigitalCompareEventSource(EPWM2_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM2_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // DCAEVT1 Force Sync Signal EPWM_setDigitalCompareEventSource(EPWM2_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM2_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0; // DCAEVT2 Force Sync Signal EPWM_enableDigitalCompareADCTrigger(EPWM2_BASE, EPWM_DC_MODULE_A); EPWM_enableDigitalCompareSyncEvent(EPWM2_BASE, EPWM_DC_MODULE_B); EPWM_setDigitalCompareEventSource(EPWM2_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM2_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // DCAEVT1 Force Sync Signal EPWM_setDigitalCompareEventSource(EPWM2_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM2_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0; // DCAEVT2 Force Sync Signal EPWM_enableDigitalCompareADCTrigger(EPWM2_BASE, EPWM_DC_MODULE_B); EPWM_selectDigitalCompareTripInput(EPWM2_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH); EPWM_selectDigitalCompareTripInput(EPWM2_BASE, EPWM_DC_TRIP_TRIPIN2, EPWM_DC_TYPE_DCAL); EPWM_selectDigitalCompareTripInput(EPWM2_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH); EPWM_selectDigitalCompareTripInput(EPWM2_BASE, EPWM_DC_TRIP_TRIPIN2, EPWM_DC_TYPE_DCBL); EPWM_setTripZoneDigitalCompareEventCondition(EPWM2_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH); EPWM_setTripZoneDigitalCompareEventCondition(EPWM2_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DC_DISABLED); EPWM_setTripZoneDigitalCompareEventCondition(EPWM2_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH); EPWM_setTripZoneDigitalCompareEventCondition(EPWM2_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DC_DISABLED); EPWM_disableDigitalCompareBlankingWindow(EPWM2_BASE); EPWM_disableDigitalCompareWindowInverseMode(EPWM2_BASE); EPWM_setDigitalCompareBlankingEvent(EPWM2_BASE,EPWM_DC_WINDOW_START_TBCTR_ZERO); EPWM_setDigitalCompareFilterInput(EPWM2_BASE, EPWM_DC_WINDOW_SOURCE_DCAEVT1); EPWM_setDigitalCompareWindowOffset(EPWM2_BASE, 0); EPWM_setDigitalCompareWindowLength(EPWM2_BASE, 0); EPWM_disableDigitalCompareCounterCapture(EPWM2_BASE); EPWM_setupEPWMLinks(EPWM2_BASE,EPWM_LINK_WITH_EPWM_1,EPWM_LINK_TBPRD); EPWM_setupEPWMLinks(EPWM2_BASE,EPWM_LINK_WITH_EPWM_1,EPWM_LINK_COMP_A); EPWM_setupEPWMLinks(EPWM2_BASE,EPWM_LINK_WITH_EPWM_1,EPWM_LINK_COMP_B); EPWM_setupEPWMLinks(EPWM2_BASE,EPWM_LINK_WITH_EPWM_1,EPWM_LINK_COMP_C); EPWM_setupEPWMLinks(EPWM2_BASE,EPWM_LINK_WITH_EPWM_1,EPWM_LINK_COMP_D); HRPWM_setOutputSwapMode(EPWM2_BASE,false);// not swapped; HRPWM_setChannelBOutputPath(EPWM2_BASE, HRPWM_OUTPUT_ON_B_NORMAL); // not swapped; //driverlib bugs? /* HRPWM_setDeadbandMEPEdgeSelect(EPWM1_BASE, HRPWM_DB_MEP_CTRL_RED_FED); HRPWM_setMEPControlMode(EPWM1_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_setMEPControlMode(EPWM1_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_setCounterCompareShadowLoadEvent(EPWM1_BASE, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_enablePeriodControl(EPWM1_BASE); HRPWM_enableAutoConversion(EPWM1_BASE); HRPWM_disablePhaseShiftLoad(EPWM1_BASE); */ EALLOW; EPwm2Regs.HRCNFG.all = 0x0; EPwm2Regs.HRCNFG.bit.EDGMODE = 3; // MEP control on both edges EPwm2Regs.HRCNFG.bit.EDGMODEB = 3; // MEP control on both edges EPwm2Regs.HRCNFG.bit.CTLMODE = 0; EPwm2Regs.HRCNFG.bit.CTLMODEB = 0; EPwm2Regs.HRCNFG.bit.HRLOAD = 0; //Update at Zero EPwm2Regs.HRCNFG.bit.AUTOCONV = 1; // Enable auto-conversion logic EPwm2Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control. EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 1 ; // TBPHSHR Load Enable EDIS; // // Interrupt where we will change the Compare Values // Select INT on Time base counter zero event, // Enable INT, generate INT on 3rd event // //EPWM_setInterruptSource(EPWM2_BASE, EPWM_INT_TBCTR_ZERO); /* Generate Interrupt on 1st even*/ //EPWM_setInterruptEventCount(EPWM2_BASE, 2U); EPWM_disableInterrupt(EPWM2_BASE); } void Initialize_EPWM3() { // // Set-up TBCLK // EPWM_setTimeBasePeriod(EPWM3_BASE, 20000); // EPwm4Regs.TBPRD = 20000; // Time Base Period Register //EPWM_setPhaseShift(EPWM3_BASE, 0U); EPWM_setTimeBaseCounter(EPWM3_BASE, 0U); // EPwm4Regs.TBCTL.bit.CTRMODE = 0; // Counter Mode // // Freeze the counter // EPWM_setTimeBaseCounterMode(EPWM3_BASE, EPWM_COUNTER_MODE_STOP_FREEZE); // // Set up counter mode // EPWM_setTimeBaseCounterMode(EPWM3_BASE, EPWM_COUNTER_MODE_UP_DOWN); EPWM_enablePhaseShiftLoad(EPWM3_BASE); EPWM_setClockPrescaler(EPWM3_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); //Sync signal Output is at Counter ZERO. EPWM_setSyncOutPulseMode(EPWM3_BASE, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN); // EPwm4Regs.TBCTL.bit.SYNCOSEL = 0; // Sync Output Select EPWM_selectPeriodLoadEvent(EPWM3_BASE, EPWM_SHADOW_LOAD_MODE_SYNC); // (*ePWM[2]).TBCTL2.bit.PRDLDSYNC = 2; // Shadow to Active when SYC received // // Set up shadowing // // EPWM_setCounterCompareShadowLoadMode(EPWM3_BASE, EPWM_COUNTER_COMPARE_A, // EPWM_COMP_LOAD_ON_CNTR_ZERO); // EPWM_setCounterCompareShadowLoadMode(EPWM3_BASE, EPWM_COUNTER_COMPARE_B, // EPWM_COMP_LOAD_ON_CNTR_ZERO); // // Set actions // EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); //Set Period load mode. EPWM_setPeriodLoadMode(EPWM3_BASE, EPWM_PERIOD_SHADOW_LOAD); EPWM_selectPeriodLoadEvent(EPWM3_BASE, EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO); EPWM_setActionQualifierShadowLoadMode(EPWM3_BASE, EPWM_ACTION_QUALIFIER_A, EPWM_AQ_LOAD_ON_CNTR_ZERO); // EPwm4Regs.AQCTL.bit.SHDWAQAMODE = 1; // set shadow mode // EPwm4Regs.AQCTL.bit.LDAQASYNC = 0; // set shadow mode EPWM_setActionQualifierShadowLoadMode(EPWM3_BASE, EPWM_ACTION_QUALIFIER_B, EPWM_AQ_LOAD_ON_CNTR_ZERO); // EPwm4Regs.AQCTL.bit.SHDWAQBMODE = 1; // set shadow mode // EPwm4Regs.AQCTL.bit.LDAQBSYNC = 0; // set shadow mode EPWM_setActionQualifierContSWForceShadowMode( EPWM3_BASE, EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierContSWForceShadowMode( EPWM3_BASE, EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO); /* EPWM_setActionQualifierT1TriggerSource( EPWM3_BASE,EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1); // EPwm4Regs.AQTSRCSEL.bit.T1SEL = 2; EPWM_setActionQualifierT2TriggerSource( EPWM3_BASE,EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1); // EPwm4Regs.AQTSRCSEL.bit.T2SEL = 0; */ // // Set Compare values // EPWM_setCounterCompareValue(EPWM3_BASE, EPWM_COUNTER_COMPARE_A, 0); EPWM_setCounterCompareValue(EPWM3_BASE, EPWM_COUNTER_COMPARE_B, 0); EPWM_setDeadBandCounterClock(EPWM3_BASE, EPWM_DB_COUNTER_CLOCK_HALF_CYCLE); EPWM_setRisingEdgeDelayCount(EPWM3_BASE, 80); EPWM_setFallingEdgeDelayCount(EPWM3_BASE, 80); //OUT mode EPWM_setDeadBandDelayMode(EPWM3_BASE, EPWM_DB_RED, true); EPWM_setDeadBandDelayMode(EPWM3_BASE, EPWM_DB_FED, true); //IN_MODE EPWM_setRisingEdgeDeadBandDelayInput(EPWM3_BASE, EPWM_DB_INPUT_EPWMA); EPWM_setFallingEdgeDeadBandDelayInput(EPWM3_BASE, EPWM_DB_INPUT_EPWMA); EPWM_setDeadBandDelayPolarity(EPWM3_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH); // xB is inverted EPWM_setDeadBandDelayPolarity(EPWM3_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW); // // // // //EPWM_setADCTriggerSource(EPWM3_BASE,EPWM_SOC_A,EPWM_SOC_TBCTR_ZERO); //EPWM_setADCTriggerSource(EPWM3_BASE, EPWM_SOC_B, EPWM_SOC_DCxEVT1); /* Generate pulse on 1st even*/ //EPWM_setADCTriggerEventPrescale(EPWM3_BASE, EPWM_SOC_A, 1); //EPWM_setADCTriggerEventPrescale(EPWM3_BASE, EPWM_SOC_B, 1); /* Enable SOC on A group*/ //EPWM_enableADCTrigger(EPWM3_BASE, EPWM_SOC_A); /* Enable SOC on B group*/ // EPWM_enableADCTrigger(EPWM3_BASE, EPWM_SOC_B); EPWM_enableGlobalLoadRegisters( EPWM3_BASE, EPWM_GL_REGISTER_AQCTLA_AQCTLA2 | EPWM_GL_REGISTER_AQCTLB_AQCTLB2 | EPWM_GL_REGISTER_TBPRD_TBPRDHR | EPWM_GL_REGISTER_CMPA_CMPAHR | EPWM_GL_REGISTER_CMPB_CMPBHR); EPWM_setGlobalLoadEventPrescale(EPWM3_BASE, 1); EPWM_setGlobalLoadTrigger(EPWM3_BASE, EPWM_GL_LOAD_PULSE_GLOBAL_FORCE); EPWM_enableGlobalLoadOneShotMode(EPWM3_BASE); EPWM_enableGlobalLoad(EPWM3_BASE); /* EPWM_enableTripZoneSignals(EPWM3_BASE, EPWM_TZ_SIGNAL_OSHT1 | EPWM_TZ_SIGNAL_OSHT2); EPWM_setTripZoneAction(EPWM3_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(EPWM3_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(EPWM3_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(EPWM3_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(EPWM3_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(EPWM3_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE); EPWM_disableTripZoneInterrupt( EPWM3_BASE, EPWM_TZ_INTERRUPT_CBC | EPWM_TZ_INTERRUPT_OST | EPWM_TZ_INTERRUPT_DCAEVT1 | EPWM_TZ_INTERRUPT_DCAEVT2 | EPWM_TZ_INTERRUPT_DCBEVT1 | EPWM_TZ_INTERRUPT_DCBEVT2); EPWM_enableTripZoneInterrupt(EPWM3_BASE, EPWM_TZ_INTERRUPT_OST); */ EPWM_disableDigitalCompareSyncEvent(EPWM3_BASE, EPWM_DC_MODULE_A); EPWM_setDigitalCompareEventSource(EPWM3_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM3_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // DCAEVT1 Force Sync Signal EPWM_setDigitalCompareEventSource(EPWM3_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM3_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0; // DCAEVT2 Force Sync Signal EPWM_enableDigitalCompareADCTrigger(EPWM3_BASE, EPWM_DC_MODULE_A); EPWM_enableDigitalCompareSyncEvent(EPWM3_BASE, EPWM_DC_MODULE_B); EPWM_setDigitalCompareEventSource(EPWM3_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM3_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // DCAEVT1 Force Sync Signal EPWM_setDigitalCompareEventSource(EPWM3_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareEventSyncMode(EPWM3_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED); //EPwm4Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0; // DCAEVT2 Force Sync Signal EPWM_enableDigitalCompareADCTrigger(EPWM3_BASE, EPWM_DC_MODULE_B); EPWM_selectDigitalCompareTripInput(EPWM3_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH); EPWM_selectDigitalCompareTripInput(EPWM3_BASE, EPWM_DC_TRIP_TRIPIN2, EPWM_DC_TYPE_DCAL); EPWM_selectDigitalCompareTripInput(EPWM3_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH); EPWM_selectDigitalCompareTripInput(EPWM3_BASE, EPWM_DC_TRIP_TRIPIN2, EPWM_DC_TYPE_DCBL); EPWM_setTripZoneDigitalCompareEventCondition(EPWM3_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH); EPWM_setTripZoneDigitalCompareEventCondition(EPWM3_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DC_DISABLED); EPWM_setTripZoneDigitalCompareEventCondition(EPWM3_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH); EPWM_setTripZoneDigitalCompareEventCondition(EPWM3_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DC_DISABLED); EPWM_disableDigitalCompareBlankingWindow(EPWM3_BASE); EPWM_disableDigitalCompareWindowInverseMode(EPWM3_BASE); EPWM_setDigitalCompareBlankingEvent(EPWM3_BASE, EPWM_DC_WINDOW_START_TBCTR_ZERO); EPWM_setDigitalCompareFilterInput(EPWM3_BASE, EPWM_DC_WINDOW_SOURCE_DCAEVT1); EPWM_setDigitalCompareWindowOffset(EPWM3_BASE, 0); EPWM_setDigitalCompareWindowLength(EPWM3_BASE, 0); EPWM_disableDigitalCompareCounterCapture(EPWM3_BASE); EPWM_setupEPWMLinks(EPWM3_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD); EPWM_setupEPWMLinks(EPWM3_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A); EPWM_setupEPWMLinks(EPWM3_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_B); EPWM_setupEPWMLinks(EPWM3_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_C); EPWM_setupEPWMLinks(EPWM3_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_D); HRPWM_setOutputSwapMode(EPWM3_BASE, false); // not swapped; HRPWM_setChannelBOutputPath(EPWM3_BASE, HRPWM_OUTPUT_ON_B_NORMAL); // not swapped; EALLOW; EPwm3Regs.HRCNFG.all = 0x0; EPwm3Regs.HRCNFG.bit.EDGMODE = 3; // MEP control on both edges EPwm3Regs.HRCNFG.bit.EDGMODEB = 3; // MEP control on both edges EPwm3Regs.HRCNFG.bit.CTLMODE = 0; EPwm3Regs.HRCNFG.bit.CTLMODEB = 0; EPwm3Regs.HRCNFG.bit.HRLOAD = 0; //Update at Zero EPwm3Regs.HRCNFG.bit.AUTOCONV = 1; // Enable auto-conversion logic EPwm3Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control. EPwm3Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // TBPHSHR Load Enable EDIS; // // Interrupt where we will change the Compare Values // Select INT on Time base counter zero event, // Enable INT, generate INT on 3rd event // //EPWM_setInterruptSource(EPWM3_BASE, EPWM_INT_TBCTR_ZERO); /* Generate Interrupt on 1st even*/ //EPWM_setInterruptEventCount(EPWM3_BASE, 2U); EPWM_disableInterrupt(EPWM3_BASE); } //void Initialize_EPWM7() //{ // /*** Initialize ePWM2 modules ***/ // { // /*-- Setup Action-Qualifier (AQ) Submodule --*/ // EPwm7Regs.AQCTLA.all = 0; // Action Qualifier Control Register For Output A // EPwm7Regs.AQCTLB.all = 0; // Action Qualifier Control Register For Output B // // Action Qualifier Software Force Register // EPwm8Regs.AQSFRC.bit.RLDCSF = 3; // immediately load //// EPwm8Regs.AQSFRC.all = (EPwm8Regs.AQSFRC.all & ~0xC0) | 0x0; // // Action Qualifier Continuous S/W Force Register // EPwm7Regs.AQCSFRC.bit.CSFA = 1; // Continuous Low on output A // EPwm7Regs.AQCSFRC.bit.CSFB = 1; // Continuous Low on output B //// EPwm8Regs.AQCSFRC.all = (EPwm8Regs.AQCSFRC.all & ~0xF) | 0x0; // asm(" EALLOW"); // EPwm7Regs.TZSEL.bit.OSHT1 = 1; // Trip Zone Select Register // EPwm7Regs.TZSEL.bit.OSHT2 = 1; // Trip Zone Select Register //// EPwm8Regs.TZSEL.all = 32768; // Trip Zone Select Register // /* // Trip Zone Control Register // EPwm8Regs.TZCTL.bit.TZA = 2; // TZ1 to TZ6 Trip Action On EPWM1A // EPwm8Regs.TZCTL.bit.TZB = 2; // TZ1 to TZ6 Trip Action On EPWM1B // EPwm8Regs.TZCTL.bit.DCAEVT1 = 3; // EPWM1A action on DCAEVT1 // EPwm8Regs.TZCTL.bit.DCAEVT2 = 3; // EPWM1A action on DCAEVT2 // EPwm8Regs.TZCTL.bit.DCBEVT1 = 3; // EPWM1B action on DCBEVT1 // EPwm8Regs.TZCTL.bit.DCBEVT2 = 3; // EPWM1B action on DCBEVT2 // */ // EPwm7Regs.TZCTL.all = (EPwm8Regs.TZCTL.all & ~0xFFF) | 0xFFA; // /* // Trip Zone Enable Interrupt Register // EPwm8Regs.TZEINT.bit.OST = 0; // Trip Zones One Shot Int Enable // EPwm8Regs.TZEINT.bit.CBC = 0; // Trip Zones Cycle By Cycle Int Enable // EPwm8Regs.TZEINT.bit.DCAEVT1 = 0; // Digital Compare A Event 1 Int Enable // EPwm8Regs.TZEINT.bit.DCAEVT2 = 0; // Digital Compare A Event 2 Int Enable // EPwm8Regs.TZEINT.bit.DCBEVT1 = 0; // Digital Compare B Event 1 Int Enable // EPwm8Regs.TZEINT.bit.DCBEVT2 = 0; // Digital Compare B Event 2 Int Enable // */ // EPwm7Regs.TZEINT.bit.OST = 1; // Trip Zones One Shot Int Enable //// EPwm8Regs.TZEINT.all = (EPwm8Regs.TZEINT.all & ~0x7E) | 0x0; // asm(" EDIS"); // // } //}
Best regards,
Hiroyuki Onishi
Hi Onishi-san,
Here's a description of the TRREM register:
This value keeps track of the remainder portion of the HRPWM hardware calculations.
Notes:
[1] The lower 8-bits of the TRREM register can be automatically initialized with the TBPHSHR value on a SYNCIN or TBCTL[SWFSYNC] event or DC event (if enabled). The user can also write a value with the CPU.
[2] Priority of TRREM register updates:
Sync (software or hardware) TBPHSHR copied to TRREM Highest Priority
HRPWM Hardware (updates TRREM register) Next priority
CPU Write To TRREM Register Lowest Priority
The C2000Ware example mentioned in the following post is the best place to find out how to use this register in your code.
CCS/TMS320F28379D: HRPWM Question - C2000 microcontrollers forum - C2000™︎ microcontrollers - TI E2E...
I hope this helps.
Hrishi
Hi Hrishi-san,
Thank you very much for your quick reply.
The example and your post is helpful for understanding TRREM register.
Let me ask you another question.
When I test the example without sweep operation, rare jittering still exists.
Can I avoid this jittering?
yellow : EPWM1 - A, blue EPWM2 - A
Best regards,
Hiroyuki Onishi
Hi Hrishi-san,
I'd like to attach another picture and other information.
・>How are you stopping the sweep?
I cannot get this picture when oscilloscope setting is standard.
After enabling Persistence function of oscilloscope, I got this results.
・>How often do you see this jitter?
only one pulse in ten seconds.
・>Do you see it every time you stop the sweep or only sometimes and at random points (randow TBPRD, values)?
I tested following 3 parameters and all results have jittering.
-TBPRD : 50, TBPRDHR : 128 << 8
-TBPRD : 70, TBPRDHR : 64 << 8
-TBPRD : 100, TBPRDHR : 20 << 8
・>which device are you testing this with?
I tested following 2 control card.
TMDSCNCD28379D : jitter found.
TMDSCNCD280049C: no jitter. (soucecode is ported form 2837xd example code.)
・>Have you modified anything at all in the example?
I'd like to attach 2 project folder.
hrpwm_deadband_sfo_cpu01.ziphrpwm_deadband_sfo_cpu01_F280049M.zip
The main change is to remove sweep for loop.
If you need any other information, please let me know.
Best regards,
Hiroyuki Onishi
Onishi-san,
Thank you for providing this information.
It looks like the PWM period value is only 70 counts in your code. Please change this back to the minimum period value (360d) that is used in the example project. The reason for this is that there is some time-critical code that needs to execute in a synchronized fashion with respect to the PWM switching cycle. If the PWM period is too small, the time critical code execution may not meet timing requirements with respect to the switching cycle. This might be the reason why you see jitter on the PWM output. The example code restricts the minimum period for this reason. You could optimize the time-critical code and/or move it to the CLA to push this restriction further i.e. allow higher switching frequency.
I hope this helps.
Hrishi
Hrishi-san,
Thank you for your advice.
I tried to increase TBPRD to (400d) and set TBPRDHR to (360d << 8) with TMDSCNCD280049C . Jitter is still found in waveform, so I watched TRREM register value to check what is going on.
Whenever I set TRREM register in sourcecode, TRREM register value is automatically over-written in each PWM cycles. If the difference between over-writed TRREM register value and coded TRREM register value (higher than about 150d or 200d),jittering seems occuring.
I think current method is not suitable for smooth transition in high freaquency operation, so I'd like to try to find another method.
I understand a lot of things about TRREM, and I'd wolud like to close this thread.
Thank you very much for your help. When I have questions about another method, I will post new thread.
Best reagards,
Hiroyuki Onishi