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Hi,
In previous discussion about the issues related to HR phase update to synchronize ePWM I was pointed to use TRREM register for HR phase update instead of TBHPSHR.
I went through the latest TRM and the example in C2000Ware (<C2000Ware_Dir>\device_support\f2837xd\examples\cpu1\hrpwm_deadband_sfo_v8) to understand the usage of TRREM.
In the TRM, the register description is as below
" 1. The lower 8-bits of the TRREM register can be automatically initialized with the TBPHSHR value on a SYNCIN or TBCTL[SWFSYNC] event or DC event (if enabled). The user can also write a value with the CPU.
2. Priority of TRREM register updates:
Sync (software or hardware) TBPHSHR copied to TRREM : Highest Priority
HRPWM Hardware (updates TRREM register): Next priority
CPU Write To TRREM Register: Lowest Priority
3. Bit 10 of TRREM register is not used in asymmetrical mode. This bit can be forced to zero."
I have few question on the explanation above
1) If we are supposed to just use 8-bits of HR phase in TRREM it is not very clear what is the use of the rest 3-bits in 11-bit register.
2) It says we can automatically initialize the TRREM register from TBPHSHR register. What is the procedure to enable this feature? If we can do this what is the need to perform software write on TRREM register through CPU?
3) What does "HRPWM Hardware(updates TRREM register)" mean? What are the settings that will cause this updates?
Also I ran the example hrpwm_deadband_sfo_v8 on hardware, I need some clarifications on the settings in the example to understand the usage of TRREM
1) For the HR phase calculation the following operations are performed. I understand that the period value is converted to 8-bit fraction value and then divided by value of 2. This value is then subtracted from 0xFF. Why do we need to do the subtraction from 0xFF?
switch(PeriodOdd)
{
case 1:
//
// Accounting for divide by 2 = 0.5
//
PhaseFine2 = 0xFF - (PeriodFine >> 9) - 0x7F;
break;
default:
PhaseFine2 = 0xFF - (PeriodFine >> 9);
break;
}
2) The final REM value is then calculated by following operation. Why do we need to add the value of 0x100 for the phase? When we are just concerned with only 8-bit value of TBHPS to update the TRREM register why the 9th bit is set here?
temp_REM2 = (Uint16) 0x100 + PhaseFine2;
3) In the ISR PRDEQfix_ISR, both ePWM1 and 2 values are updated, ePWM2 TRREM is updated with the calculated as explained above and ePWM1 TRREM value is updated with 0x100. What is the need to update the TRREM register for ePWM1 when the TBPHS value for ePWM1 is set to 0?
4) When I set breakpoint at the end of ISR with ePWM TBCTL register set to free run and try to observe the TRREM register, I see it is updated continuously and does not have the value we set in ISR. Who updates this register? Is there any way to disable the update?
Please provide the above clarifications so that I can have much better understanding on this register so that I can use it effectively for the application.
Thanks,
Aditya
