After trying and failing to configure the ePWM and HPWM to implement center aligned, symmetric high resolution duty cycle control, I found this post, which seems to work. However I cannot understand why it works. In fact, based on how I choose to interpret the documentation and various other related posts, this actually shouldn't be possible.
Here's my current thought process:
1. To get symmetric output, the leading and trailing edges have to be shifted by equal amounts, but in opposite direction. For example if I want to decrease the pulse width by half of a TBCLK period, I would have to delay the leading edge by 0.25 TBCLK (~64 MEP ticks) and advance (negative delay) the trailing edge by 0.25 TBCLK (~64 MEP ticks).
2. The delay on the leading edge is straightforward, but the HRPWM can't actually advance an edge (causality and all that). Instead, the trailing edge is advanced by having the course ePWM output shifted one whole TBCLK period earlier, and adding a delay of 0.75 TBCLK with the HRPWM (~192 MEP ticks).
3. Each ePWM output has only one delay associated with it (CMPAHR for ePWMxA, CMPBHR for ePWMxB). Therefore it shouldn't be possible to generate the differing HR leading and falling edge delays required.
Obviously I'm wrong, but I can't tell where. Are there actually multiple HR delays for each output channel? Or perhaps the CMPAHR value is actually inverted when counting down? Either way, what in the linked example code sets up such sophisticated behavior?