TMS320F280049: How to evaluate max PWM ISR Latency

Benjamin Zhou

Part Number: TMS320F280049

Hi Team,

Could you kindly help on the F280049 ISR latency not constant issue? thanks.F280049 PWM ISR latency issue.docx

Issue description:

My customer used 280049 to control digital power. And trigger an interrupt (ISR) by setting EPWM compare value. And found that the latency (delay time) was not constant which will influence customer’s control strategy seriously.

Test Procedure:

1. The ISR code was written by ASM, the latency was tested by setting breakpoint before executing context save as blow figure. And found this latency (delay time) by watching the TBCTR register, the TBCTR shown that the latency is about >300ns;

2. To remove the factor of online simulation by XDC100v3, we use GPIO output status by make the chip run alone. So we further confirmed the issue of interrupt latency.

Support Need:

Which factors would impact the latency for the ISR between interrupt triggered and ISR executive? Is the latency fixed or flexible?
How to achieve the minimum latency for the ISR configure or which part should be pay attention for the software configuration?

over 7 years ago

0 Nima Eskandari over 7 years ago

TI__Guru 52040 points

Ben, I am researching this and will get back to you!

0 Kris Parrent over 7 years ago

Intellectual 860 points

Benjamin,

A few things to keep in mind- higher priority ISRs will always be served first. If you take a look at the PIE table, see if you are using any ISRs with higher priority than the EPWM ISR. Depending which EPWM module you are using, you may want to switch to one with a higher priority ISR.

If another ISR is already active, I believe that ISR will complete prior to any pending ISR being serviced. Not totally sure about that, but you could check it pretty easily.

Some instructions are un-interruptable and will leave an ISR pending until completed. One example of this is the RPT instruction. There are more but I don't know them right off hand. They should be outlined in the C28x Instruction Set manual.

-----

The most likely culprit in my opinion is the execution of another ISR. Take a look at your other ISRs and do some GPIO toggling in those to see what is active when you see a delayed ISR.

Regards,
Kris

0 Nima Eskandari over 6 years ago in reply to Kris Parrent

TI__Guru 52040 points

Benjamin,

Did Kris' reply solve the issue?

Nima

0 Benjamin Zhou over 6 years ago in reply to Nima Eskandari

TI__Expert 4000 points

Hi Kris, Nima,
Sorry for reply later because of holiday things.

Some questions still existed:
1. For this issue, during the test, only enabled single interrupt and disabled the watchdog. so there is no other higher priority ISR would be server.
2. During the test, there is no BIOS system, when add some source code at main() prototype, the latency for the ISR would be changed,
main()
{
...
while(1)
{
//add some source code
}
}
3. We also tried another single ISR, the same things happened.

could you kindly give comments on how to evaluate the ISR latency? or what's your comments for the maximum latency for ISR? This issue is very critical as there are some control loop required precious timing.

Expect for your reply, thanks.

Best Regards
Benjamin