TMS320F28377S: Multi-word McBSP frames for SPI

  // McBSP register settings
  pmcbsp->reg->SPCR2.all =
      0x0000;  // Reset FS generator, sample rate generator & transmitter
  pmcbsp->reg->SPCR1.all =
      0x0000;  // Reset Receiver, Right justify word, Digital loopback dis.

  // Transmit frame synchronization is generated internally by the
  // sample Rate generator
  pmcbsp->reg->PCR.bit.FSXM = 1;
  // Receive frame synchronization is supplied by the sample rate generator
  pmcbsp->reg->PCR.bit.FSRM = 1;
  // Internal MCLKR is driven by the sample rate generator of the McBSP
  pmcbsp->reg->PCR.bit.CLKRM = 1;
  // Internal CLKX is driven by the sample rate generator of the McBSP
  pmcbsp->reg->PCR.bit.CLKXM = 1;
  // SCLKME is used in conjunction with the CLKSM bit to select the input
  // clock.
  pmcbsp->reg->PCR.bit.SCLKME = 0;
  pmcbsp->reg->RCR2.bit.RDATDLY =
      1;  // FSX setup time 1 in master mode. 0 for slave mode (Receive)
  pmcbsp->reg->XCR2.bit.XDATDLY =
      1;  // FSX setup time 1 in master mode. 0 for slave mode (Transmit)

  pmcbsp->reg->SPCR1.bit.CLKSTP = 2;  // SPI mode, no delay
  pmcbsp->reg->PCR.bit.CLKXP = 0;  // low inactive state, xmit on rising edge
  pmcbsp->reg->PCR.bit.CLKRP = 0;  // rcv falling edge

  pmcbsp->reg->XCR2.bit.XPHASE = 0;
  pmcbsp->reg->RCR2.bit.RPHASE = 0;

  pmcbsp->reg->XCR1.bit.XFRLEN1 = 0;
  pmcbsp->reg->RCR1.bit.RFRLEN1 = 0;

  // set read word length
  pmcbsp->reg->RCR1.bit.RWDLEN1 = 2;
  // set write word length
  pmcbsp->reg->XCR1.bit.XWDLEN1 = 2;

  pmcbsp->reg->SRGR2.bit.CLKSM = 1;  // CLKSM=1

  pmcbsp->reg->SRGR1.all = baudrate;  //  CLKGDV=x

  pmcbsp->reg->SPCR2.bit.GRST = 1;  // Enable the sample rate generator

  delay()

  pmcbsp->reg->SPCR2.bit.XRST = 1;  // Release TX from Reset
  pmcbsp->reg->SPCR1.bit.RRST = 1;  // Release RX from Reset
  pmcbsp->reg->SPCR2.bit.FRST = 1;  // Frame Sync Generator reset
  
  delay()

Hi,

Not sure if this belongs in this post or should be moved, but I am trying to send 16 16bit data over one chip select period, but the mcbsp seems to be breaking it up into 32 bits at a time. Could you suggest what could be going wrong?

Rohit.

Mark,

When i try writing the DXR1 register only. The total message count is 32 instead of 16 but the spi frame length is still 32 as shown in logic analyzer image.

if (txcnt[mcbsp_index] < numtx) {  
  pmcbsp->reg->DXR1.all = *pmcbsp->ptxbuff;
  pmcbsp->ptxbuff++;
  txcnt[mcbsp_index]++;
}

Rohit.

Can you dump your McBSP register configurations into the Mcbsp spi loopback example and just try the simple loopback?

the only setting in your configuration i don't see matching the required configuration is setting FSXP to 1. but this should not have any impact on the your current issue.

After you write to DXR1, do you have other code that ensures that the word is transmitted before transmitting another 16 bits?
-Mark

After writing to DXR1, I wait to read DRR and then send the next word. I think this is where the problem is.

It sounds like you are following the proper procedure.

Were you able to test out my recommendation?
Can you ensure that XFRLEN2 and RFRLEN2 are both 0 as well?

-Mark

Hi Mark,

I used the example program with my config and it is working as expected. See screenshot. I am confused what could be going on.

Rohit.

    McbspbRegs.SPCR2.all = 0x0000;       // Reset FS generator, sample rate
                                         // generator & transmitter
    McbspbRegs.SPCR1.all = 0x0000;       // Reset Receiver, Right justify word,

    // Transmit frame synchronization is generated internally by the
    // sample Rate generator
    McbspbRegs.PCR.bit.FSXM = 1;
    // Receive frame synchronization is supplied by the sample rate generator
    McbspbRegs.PCR.bit.FSRM = 1;
    // Internal MCLKR is driven by the sample rate generator of the McBSP
    McbspbRegs.PCR.bit.CLKRM = 1;
    // Internal CLKX is driven by the sample rate generator of the McBSP
    McbspbRegs.PCR.bit.CLKXM = 1;
    // SCLKME is used in conjunction with the CLKSM bit to select the input
    // clock.
    McbspbRegs.PCR.bit.SCLKME = 0;

    //McbspbRegs.PCR.bit.FSXP = 1;

    McbspbRegs.RCR2.bit.RDATDLY =
        1;  // FSX setup time 1 in master mode. 0 for slave mode (Receive)
    McbspbRegs.XCR2.bit.XDATDLY =
        1;  // FSX setup time 1 in master mode. 0 for slave mode (Transmit)

    McbspbRegs.SPCR1.bit.CLKSTP = 2;  // SPI mode, no delay
    McbspbRegs.PCR.bit.CLKXP =
          0;  // low inactive state, xmit on rising edge
    McbspbRegs.PCR.bit.CLKRP = 0;  // rcv falling edge

    McbspbRegs.RCR1.bit.RWDLEN1 = 2;     // 32-bit word
    McbspbRegs.XCR1.bit.XWDLEN1 = 2;     // 32-bit word

    McbspbRegs.SRGR2.bit.CLKSM = 1;  // CLKSM=1
    McbspbRegs.SRGR1.all = (Uint16)((200/2) + 0.5f);
    McbspbRegs.SPCR2.bit.GRST = 1;       // Enable the sample rate generator
    delay_loop();                        // Wait at least 2 SRG clock cycles
    McbspbRegs.SPCR2.bit.XRST = 1;       // Release TX from Reset
    McbspbRegs.SPCR1.bit.RRST = 1;       // Release RX from Reset
    McbspbRegs.SPCR2.bit.FRST = 1;       // Frame Sync Generator reset

I think that your next move is to start comparing line by line between the McBSP portions of the two programs.
are you inadvertently reconfiguring the McBSP module before you begin transmitting in your application?

-Mark

So I copied the config i sent you in my last message into my firmware and it works. Does the sequence of configuration matter?

Rohit,

I am glad that you figured it out. Though I don't see the difference in this configuration you shared.

Which length was the issue? from your original code, the McBSP had the correct word length...

-Mark

Sorry, must have mistyped it. the second one should have RCR1 = 160, XCR1 = 160 and SRGR1 = 1