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TMS320F28379S: Watchdog Timer Reset on OSCCLK drop and WDCR

Chad Coates
Prodigy 20 points
Part Number: TMS320F28379S

Have two questions about the internal Watchdog Timer function:

1. If the OSCCLK drops out, does the Watchdog Reset assert (WDRST)?

2. How is the Watchdog Configuration Register (WDCR) accessed and can it be accessed during runtime? In other words, is there a way for the processor to disable its own Watchdog Timer due to a malfunction or corrupted code?

Thanks.

  • 0
    TI__Genius 17849 points
    Chad,

    Please check out the watchdog chapter (2.9), pg 113, in the F2837xS Technical Reference Manual (www.ti.com/.../spruhx5e.pdf). Section 2.9.3 explains more on the Watchdog Reset or Watchdog Interrupt Modes. Let me know if you have any other questions.

    Regards,
    Ozino
  • 0 in reply to Ozino Odharo
    Prodigy 20 points

    Ozino,

    Thanks for your response. Unfortunately the link you provided to the F2837xS Technical Reference Manual doesn't work.

    Regards,

    Chad

  • 0 in reply to Chad Coates
    TI__Guru** 113755 points

    Hi Chad,

     1. If the OSCCLK drops out, does the Watchdog Reset assert (WDRST)?

    No that would not cause reset. In that case WD counter will freeze.

     2. How is the Watchdog Configuration Register (WDCR) accessed and can it be accessed during runtime? In other words, is there a way for the processor to disable its own Watchdog Timer due to a malfunction or corrupted code?

    WDCR register is protected by EALLOW as well as WDCHK field (part of WDCR register) hence possibility of this is very-very remote.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru** 113755 points

    Also  you can find the document here,

    Vivek Singh