TMS320F28379D: 1 McBsp, 2 SPIs communication

Hey Varun,

Thanks for reaching out about this issue you are experiencing. I am looking into it now and will get back to you before End-of-Day Friday (11/30/18). In the mean time go ahead and take a look a Chapter 6: SPI Operation Using the Clock Stop Mode in the following

McBSP User Guide Document: http://www.ti.com/lit/ug/sprug80a/sprug80a.pdf.

Sections 6.6 and 6.7 discuss setting up the McBSP peripheral as a SPI Master and SPI Slave. A quick skim of the information tells me that Clock Stop Mode should probably be used which will also cause the Frame Sync Sources to be internal. I will dig a little deeper myself and let you know if I find anything further.

Respectfully,

Zackary Fleenor

Hi Zack,
We are using only McBSP for now. But I am cross checking if we can actually make this happen. I want to send data at different time or simultaneously as well on both ends. Also if this is not possible I would appreciate if we can configure it for only Master-> Slave(Rx). That's my first priority. So later we can change it to two McBSP's hopefully.

Thanks

Varun

Hi Zackary,

I think I cannot do a SPI operation and right now I am focusing on the receiving side of the McBSP without SPI operation. So I have taken the External Loopback example. I am working on TMS320F28379D launchpad.  The following changes I have made to match for 32 bit SPI message of what I am sending, please let me know if it is right.

void initReceiver(uint32_t base)
{
    //
    // Configure McBSP data behaviour.
    //

    McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, MCBSP_BITS_PER_WORD_32, 0);

    //
    // Set Rx data delay to 1 cycle.
    //
    McBSP_setRxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_1);

    //
    // Set receive sign-extension and justification mode.
    //
    McBSP_setRxSignExtension(base, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);

    //
    // Configure Rx frame-sync behaviour.
    //

    //
    // Set Rx frame sync source as external.
    //
    McBSP_setRxFrameSyncSource(base, MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE); 
    McBSP_setRxClockPolarity(MCBSPB_BASE, MCBSP_RX_POLARITY_RISING_EDGE);
   

    //
    // Disable DLB mode.
    //
    McBSP_disableLoopback(base);

    //
    // Set no external clock sync for CLKG i.e. GSYNC = 0.
    //
    McBSP_enableSRGSyncFSR(base);

    //
    // Configure Rx clock behaviour.
    //

    //
    // Set MCLKR pin as source for CLKR.
    //
    McBSP_setRxClockSource(base, MCBSP_EXTERNAL_RX_CLOCK_SOURCE);

    //
    // Set LSPCLK as input source for sample rate generator.
    //
    McBSP_setRxSRGClockSource(base, MCBSP_SRG_RX_CLOCK_SOURCE_LSPCLK);

    //
    // Set Divide down value for CLKG.
    //
    McBSP_setSRGDataClockDivider(base, 49);

    McBSP_setRxFrameSyncPolarity(MCBSPB_BASE, MCBSP_RX_FRAME_SYNC_POLARITY_LOW);

    //
    // Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
    // Total cycles required = 2*(SYSCLK/LSPCLK). In this example
    // LSPCLK = SYSCLK/4.
    //
    MCBSP_CYCLE_NOP(8);
}

Now, I am sending one 32 bit word always, out of ten tries I am reading it only once and that too with bits shifted 1 or 2 places left or right. I am giving external connection to MCLKR, MDR and FSX. Once I read a word with bit shifted I will never be able to read another word again. Did anybody have this problem before?

The SPCLKis running at 50MHz, so I used 49 divider to bring it down to 1MHz and I am sending with 1MHz as well. Let me know if you got anything

Regards

Varun

Hi Zackary,

Yes McBSP_enableSRGSyncFSR(base); function call was intentional sorry did not change the comment.

I am still having problems communicating with SPI on receiving side.  Please review my code below

void initTransmitter(uint32_t base)
{
    //
    // Right justify word.
    //


    //
    // Set Rx & Tx delay to 1 cycle.
    //
    McBSP_setTxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_0);


    //
    // Configure McBSP data behaviour: phase = 1; frame length = 1 word and
    // word length = dataSize.
    McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, MCBSP_BITS_PER_WORD_16,0);

    //
    // Configure Frame synchronization behaviour.
    //

    //
    // Enable transmit frame-sync ignore function.
    //
    McBSP_disableTxFrameSyncErrorDetection(base);

    //
    // Set Tx frame-sync source as internal.
    //
    McBSP_setTxFrameSyncSource(base, MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE);
    McBSP_setTxClockPolarity(MCBSPB_BASE, MCBSP_TX_POLARITY_FALLING_EDGE);

    //
    // Set the trigger source for internally generated frame-sync pulse.
    //
    McBSP_setTxInternalFrameSyncSource(base, MCBSP_TX_INTERNAL_FRAME_SYNC_DATA);


    //
    // Set no external clock sync for CLKG.
    //
    McBSP_enableSRGSyncFSR(base);

    //
    // Set frame-sync pulse period.
    //
    //McBSP_setFrameSyncPulsePeriod(base, 320);

    //
    // Set frame-sync pulse width.
    //
    McBSP_setFrameSyncPulseWidthDivider(base, 0);

    //
    // Configure Tx Clock behaviour.
    //

    //
    // Set LSPCLK as input source for sample rate generator.
    //
    McBSP_setTxSRGClockSource(base, MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN);

    //
    // Set CLKX source as sample rate generator.
    //
    McBSP_setTxClockSource(base, MCBSP_INTERNAL_TX_CLOCK_SOURCE);

    //
    // Set Divide down value for CLKG.
    //
    McBSP_setSRGDataClockDivider(base, 0);

    //
    // Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
    // Total cycles required = 2*(SYSCLK/LSPCLK). In this example
    // LSPCLK = SYSCLK/4.
    //
    MCBSP_CYCLE_NOP(8);
}

//
// Init Receiver - This function initialises the McBSP Receiver module.
//
void initReceiver(uint32_t base)
{
    //
    // Configure McBSP data behaviour.
    //
    McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, MCBSP_BITS_PER_WORD_16,0);


    //
    // Set Rx data delay to 1 cycle.
    //
    McBSP_setRxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_0);

    //
    // Set receive sign-extension and justification mode.
    //
    McBSP_setRxSignExtension(base, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);

    //
    // Configure Rx frame-sync behaviour.
    //

    //
    // Set Rx frame sync source as external.
    //
    McBSP_setRxFrameSyncSource(base, MCBSP_RX_EXTERNAL_FRAME_SYNC_SOURCE);
    McBSP_setRxFrameSyncPolarity(base, MCBSP_RX_FRAME_SYNC_POLARITY_LOW);
    McBSP_setRxClockPolarity(base, MCBSP_RX_POLARITY_FALLING_EDGE);


    McBSP_disableRxFrameSyncErrorDetection(base);


    //
    // Disable DLB mode.
    //
    McBSP_disableLoopback(base);

    //
    // Set no external clock sync for CLKG i.e. GSYNC = 0.
    //
    //McBSP_disableSRGSyncFSR(base);

    //
    // Configure Rx clock behaviour.
    //

    //
    // Set MCLKR pin as source for CLKR.
    //
    McBSP_setRxClockSource(base, MCBSP_EXTERNAL_RX_CLOCK_SOURCE);



    //
    // Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
    // Total cycles required = 2*(SYSCLK/LSPCLK). In this example
    // LSPCLK = SYSCLK/4.
    //
    MCBSP_CYCLE_NOP(8);
}

Trying to do SPI on receiving end. I have enabled the GSYNC so I would trigger FSG on falling edge of FSR ( which is connected to CS). I am not concerned about Tx side of McBSP for now. Now the clock is being sourced by MCLKR pin. I also used LSPCLK clock as the source dividing it by 24 to get to 1MHz. Still does not work. Is this configuration issue or the timing issue? I am asking about timing because when the FSR goes low, I am also waiting 1 clock cycle before sending out data. Tried both ways waiting and not waiting. I surely cant see the FSG signal when the FSR goes low so I am really not able to predict whats happening.

Couple of problems I have:

The data still seems to be shifting a bit here and there. 

And i set it for 1 word 16 bit, but I am receiving the word when I send 2 16 bits word so the 2nd word is being skipped. Dont know why.

Regards

Varun