TMS320F28069: Clear definition of the linked behaviour of WDFLAG, CLOCKFAIL and the XRS pin

Hello,

I have a board with a TMS320F28069 MCU, and the following circuit for the XRS and Crystal pins.
Note the intention to conform to http://processors.wiki.ti.com/index.php/WDFlag_on_Piccolo section 2B).

I am able to distinguish between watchdog, clock faillure and power on:
Watchdog triggers WDFLAG
Clock faillure triggers CLOCKFAIL
PowerOn triggers none of those two.

However, from the above linked article:
When the XRS line is pulled low, the WDFLAG bit is forced low. The WDFLAG bit will only be set if the XRS signal is sampled high after a delay of 8192 * 4 + 512 OSCLK cycles. If the XRS signal is sampled low at this time, then the WDFLAG bit will remain at 0. Therefore to distinguish between a watchdog reset and an external device reset, an external reset must be longer in duration then this sampling time.

Hence my expectation:
XRS pin Low yield WDFLAG = 0.
XRS pin High yield WDFLAG = 1, making it more of a "cold/hot reset differentiator".

What I observe is not that. Shorting the clock capacitors, causing a restart by the NMI, will reset the device with XRS pin high, without any observable glitch on the testpoint of my circuit... XRS pin IS HIGH at the ~3.7ms delay, but WDFLAG is still low.

Also, I wanted to validate our firmware for watchdog handling, and simply tied XRS to a 3.3V source BEFORE power-on of the main circuitry. WDFLAG stayed low.

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Can you please clarify all the requirement to have a set WDFLAG???
"The WDFLAG bit will only be set if the XRS signal is sampled high[...]" seems to be only half of the story.
Does it need to be triggered by the watchdog AND will be cleared automatically if XRS pin is low after 3.7ms?
I have observed CLOCKFAIL to be kept in memory after a reset... Could WDFLAG have a similar behaviour? Is there a list of other registers that are persistent after device reset?

Thanks!