TMS320F28379D: Interaction between background SFO() and interrupts/CLA tasks

I'm running high fast control loop which relies on CLA1 tasks and CPU1 ISRs running every 2.5us to update my HRPWM CMPA and CMPB registers. Like many others here have mentioned, I want to rely on SFO() for calibration but am worried about its impact on the control loop. I've found several clues scattered among other threads here, but I'd like to try and put together a more complete picture. There are two ways I'm aware of that SFO() can impact ISRs and CLA tasks:

1. SFO() accesses some of the ePWM registers. If the CLA task tries to access the ePWM registers at same time, it will stall since the CPU has priority over the CLA. The user reports delays up to 25ns (5 sysclk). No suggestion of an upper bound on this delay from TI. In that thread, Sal suggests a couple workarounds:

"You can use message RAMs. You can also use the MIRUN. The C28x can view the MIRUN register. If the CLA task is running, then the C28x should wait to access the PWM registers until the CLA task is complete."

I'm unsure of how these workarounds would work. Once SFO() is executed, how could one possibly instruct the cpu to "wait to access the PWM registers," since we cannot see or modify SFO()??

2. SFO() contains non-interruptible RPT instructions, which can increase the latency of ISRs on CPU1. User reported delays up to 100ns (25 sysclks). TI has suggested a bound of "10-30 cycles on estimate" or "about 20 cycles" (I assume these are sysclk cycles). No workarounds suggested.

While I know TI can't share many details on SFO(), I'm looking for some clear upper bounds on these latency numbers, and also assurance that there are no other routes for interaction that are being overlooked. 

Regards,

Mike

Also PS: The "ask a related question" button does not function, otherwise I would have used it for this...