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TMS320F28379D: ADC configuration for interleaved mode

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

Is it possible to configure the 4 16-bit ADCs of the TMS320F28379D to work as a single highspeed 4MSPS ADC (in interleaved mode)?

They would all be sampling the same input. When channel N completes S+H channel N+1 starts S+H in parallel with channel N continuing to perform the conversion.

Something like this:

  • Yes, I think this can be done.
    One way would be tying up 4 PWMS, that are synchronized, and have offsets from each other.
    Tie PWM1 to ADCA, PWM2 to ADCB, PWM3 to ADCC, PWM4 to ADCD.

    Start with C2000Ware device_support adc_soc_epwm example, add 2nd PWM-ADC, then 3rd, then 4th...

    Hopefully, that helps.
  • Hi Alex,

    This is inadvisable for several reasons:

    (1) The ADC-to-ADC gain error, offset error, and linearity need to be very well matched (<0.5 LSBs) for the ENOB to not degrade when interleaving. The easiest to understand is offset error: if ADC-A has +2 LSBs offset compared to the other ADCs, you will get a repeating signal every 4th conversion on top of your base signal. You could actually probably filter this one out, but the gain and linearity mismatch cause tones at less predictable locations.

    (2) As the input frequency of the 16-bit ADC increases, performance will begin to degrade when fin > about 10kHz. This is due to aperture jitter based on the jitter of the on-chip PLL. Interleaving will increase the sample rate, but won't do anything to increase the practical maximum input signal bandwidth.

    (3) The 16-bit ADCs do not support operation except in lockstep (synchronous operation). This will cause significant degradation in the ADC performance if the ADCs are set to overlap in an interleaved configuration.

    The best you can do is sample all 4 ADCs in parallel (with them running synchronously), and then average the 4 results. This will average out some of the inherent ADC noise and also average out some of the ADC non-linearity. Of course charging 4 x S+H circuits will put some additional load on the ADC signal driving circuitry.