TMS320F28379D: C2000

Hello,

C2000 processors can be clocked at a certain speed and will execute instructions at a certain rate. These instructions will lead to an effective throughput (measured in MIPS).

Depending on the sample rate at which your filters need to operate, the number of taps, the data width, and the device's maximum clock speed, you will be able to run a certain number of filtering operations. For example, with the F28379D, you have 4 cores ( 2 C28x, 2 CLAs), all of them can be clocked at 200MHz. So assume you're running a 3rd order IIR, using 16-bit data and filter coefficients, and are clocking the devices at 200MHz. You'll need approx. 8 Multiply and Accumulates (MACs) per filter output i.e. 4 instructions (assuming you'll use the dual MAC DMAC instruction).

The next variable that comes into question is the rate at which the filtering is occurring. Assume that this is at 5MHz (for example, the ADC is feeding the filters data at this rate). So, you basically have 5MHz x 4 = 20MIPS per IIR filter, with a total available 200MIPS budget. So, in theory, you could run 10 such filters "simultaneously" before the CPU or CLA runs out of steam and you run into data underrun. Counting all 4 cores, this would be 40 such filters.

And note that we haven't even considered the FFT. But I wanted to give you an idea of how you would go about thinking through this kind of design.

If this answers your question, please click on Verified Answer on my response.

Thanks,
Sira

Please clarify what you are having trouble understanding from my reply.

Thanks,
Sira

I really do need thousands or tens of thousands filter / ffts at the same time for real time processing. So what you are telling me is that it is impossible to do this now because it would take 100's of chips. Like I said I am not anywhere an expert is TI's DSP chips, is 40 filters for one chip the max there is?

Please let me know if you'd like any additional information, or if we can go ahead and close this issue.

Thanks,
Sira