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TMS320F28035: When RXERROR set, can I still receive the subsequent data or I have to reset the device?

Howard Zou
Genius 12365 points
Part Number: TMS320F28035

Hi,

in datasheet RXERROR is OR of BRKDT, FE, OE, and PE.

For either error of the above four cases, can I still receive the subsequent data or I have to reset the device to allow the following data to come in?

  • 0
    TI__Genius 17315 points
    Howard,

    RXERROR will only generate an interrupt to service the errors if the RXERRINTENA (bit 6 in SCICTL1) is set. If this is disabled (corrupted) data will continue. The RXERROR is cleared by an active SWRESET (bit 5 in SCICTL1) or by a system reset.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    TI__Genius 12365 points

    Ken,
    you mean if the interrupt is not enabled the data will continue?

    My customer doesn't use FIFO, they use SCIRXINTA interrupt service function to get the received data shown below. 

    But in F2803X TRM SPRUI10, for BRKDT 

    It is not cleared by receipt of a character after the break is detected. In order to receive more characters, the SCI must be reset by toggling
    the SW RESET bit or by a system reset.

    So I guess for FE, OE, PE, I can get the subsequent data without reset, but for BRKDT, I have to reset to get the subsequent data, right?
    Besides, why it's related to whether I set RXERRINTENA bit?

  • 0 in reply to Howard Zou
    TI__Genius 17315 points
    Howard,

    Yes, as I understand it. In order to receive more characters with a break detect condition, the SCI must first be reset by toggling the SW RESET bit or by a system reset. Note that the occurrence of a break will cause a receiver interrupt to be generated only if the RXBKINTENA (bit 1 in the SCICTL2 register) is set, NOT when the RXERRINTENA (bit 6 in SCICTL1) is set. Please see the block diagram figure 12-2 on page 730 and notice the BRKDT interrupt is controlled by RXBKINTENA, whereas the RXERROR interrupt is controlled by RXERRORINTENA.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    TI__Genius 17315 points
    Howard,

    I noticed a discrepancy between the BRKDT bit in the SCIRXST register and block diagram. After checking with the design team it turns out that the register description is correct and the block diagram has a slight error. The RXERROR is the ORing of bits 5-2 as described in the register description, which includes the bit for BRKDT. However, the BRKDT signal (BRK_DETECT) is controlled by (AND-ed with) RXBKINTEN and not RXERRINTEN, as I stated in my previous post. So in summary, the RXERROR includes the ORing with BRKDT, which is not shown in the block diagram.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken