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TMS320F28386D: How to clear CM UART RxError?

Frederick LIN
Intellectual 580 points
Part Number: TMS320F28386D

Hi,

I use CM UART module.

If I sometimes send wrong packet and get error bit FE and BE from UART_getRxError().

1. After called below process and the UARTRSR Register still with FE and BE(UART_clearRxError() not work). What is the suggested standard software reset method?

UART_clearRxError( UART0_BASE );

UART_setConfig( UART0_BASE, UART_CLK_FREQ , 921600, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE) );

UART_enableFIFO(UART0_BASE);

UART_setFIFOLevel(UART0_BASE, UART_FIFO_TX1_8, UART_FIFO_RX1_8);

2. Are the addresses of UARTRSR and UARTECR are same as 0x4000C004? The UARTRSR  Register in TRM said it's read only. But UARTECR can be write any value to clear status. It's weird.

3. I reference to the SCI SciaRegs.SCICTL1.bit.SWRESET. Calling the SysCtl_resetPeripheral(SYSCTL_PERIPH_RES_UART0) can reset all error status(see below). Is there any risk by the method?

UART_clearRxError( UART0_BASE );

SysCtl_resetPeripheral(SYSCTL_PERIPH_RES_UART0);

UART_setConfig( UART0_BASE, UART_CLK_FREQ , 921600, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE) );

UART_enableFIFO(UART0_BASE);

UART_setFIFOLevel(UART0_BASE, UART_FIFO_TX1_8, UART_FIFO_RX1_8);

Thanks

  • 0
    TI__Expert 4145 points

    Hi Frederick,

    Both UARTRSR and UARTECR registers are located at same address 0x4000C004. When a data is read from that location the content of UARTRSR is read and when write occurs on that location UARTECR is written. 

    As mentioned in the TRM any write to UARTECR should clear the error status. 

    So UART_clearRxError( UART0_BASE ); should work in your case. Please check if the error is constantly being set for the peripheral, this may be because of you setup. Please recheck the pin connections. 

    SysCtl_resetPeripheral(SYSCTL_PERIPH_RES_UART0); is only suggested in the beginning of the peripheral as after this you would have to configure all the parameters of the peripheral and also the data in the FIFO will be lost. While UART_clearRxError() will not cause the FIFO data to loose.

    Regards,

    Yashwant 

  • 0 in reply to Yashwant Temburu1
    Intellectual 580 points

    Hi Yashwant,

    Thank you, I can clear the by UART_clearRxError().

    If I call SysCtl_resetPeripheral() or UART_setConfig(), and the Uart hardware is still communicating at the same time.

    It is possible to cause getting UARTRSR  FE or BE bit when I read the next UARTDR?

    Regards,

    Frederick.

  • 0 in reply to Frederick LIN
    TI__Expert 4145 points

    Hi,

    The UART_setConfig() disables the UART and then enables it after configuration. If you enable it while there is some transmission on the bus, there may be some error set as it may not be able to detect stop bit. 

    Regards,

    Yashwant